1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s 3 4; The case below demonstrates cross block CSE of vector instructions with 5; undefined passthru operands. 6define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 7; CHECK-LABEL: foo: 8; CHECK: # %bb.0: 9; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma 10; CHECK-NEXT: vadd.vv v8, v8, v9 11; CHECK-NEXT: vs1r.v v8, (a0) 12; CHECK-NEXT: bnez a2, .LBB0_2 13; CHECK-NEXT: # %bb.1: # %falsebb 14; CHECK-NEXT: vs1r.v v8, (a1) 15; CHECK-NEXT: .LBB0_2: # %mergebb 16; CHECK-NEXT: ret 17 %a = add <vscale x 2 x i32> %x, %y 18 store <vscale x 2 x i32> %a, ptr %p1 19 br i1 %cond, label %mergebb, label %falsebb 20 21falsebb: 22 %b = add <vscale x 2 x i32> %x, %y 23 store <vscale x 2 x i32> %b, ptr %p2 24 br label %mergebb 25 26mergebb: 27 ret void 28} 29