xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v -verify-machineinstrs \
3; RUN:   --riscv-no-aliases < %s | FileCheck %s
4
5target triple = "riscv64-unknown-unknown-elf"
6
7%struct.test = type { <vscale x 1 x double>, <vscale x 1 x double> }
8
9define <vscale x 1 x double> @test(ptr %addr, i64 %vl) {
10; CHECK-LABEL: test:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    addi sp, sp, -16
13; CHECK-NEXT:    .cfi_def_cfa_offset 16
14; CHECK-NEXT:    csrrs a2, vlenb, zero
15; CHECK-NEXT:    slli a2, a2, 1
16; CHECK-NEXT:    sub sp, sp, a2
17; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
18; CHECK-NEXT:    csrrs a2, vlenb, zero
19; CHECK-NEXT:    vl1re64.v v8, (a0)
20; CHECK-NEXT:    add a0, a0, a2
21; CHECK-NEXT:    vl1re64.v v9, (a0)
22; CHECK-NEXT:    addi a0, sp, 16
23; CHECK-NEXT:    add a2, a0, a2
24; CHECK-NEXT:    vs1r.v v8, (a0)
25; CHECK-NEXT:    vs1r.v v9, (a2)
26; CHECK-NEXT:    vl1re64.v v8, (a2)
27; CHECK-NEXT:    vl1re64.v v9, (a0)
28; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
29; CHECK-NEXT:    vfadd.vv v8, v9, v8
30; CHECK-NEXT:    csrrs a0, vlenb, zero
31; CHECK-NEXT:    slli a0, a0, 1
32; CHECK-NEXT:    add sp, sp, a0
33; CHECK-NEXT:    .cfi_def_cfa sp, 16
34; CHECK-NEXT:    addi sp, sp, 16
35; CHECK-NEXT:    .cfi_def_cfa_offset 0
36; CHECK-NEXT:    jalr zero, 0(ra)
37entry:
38  %ret = alloca %struct.test, align 8
39  %val = load %struct.test, ptr %addr
40  store %struct.test %val, ptr %ret, align 8
41  %0 = load %struct.test, ptr %ret, align 8
42  %1 = extractvalue %struct.test %0, 0
43  %2 = extractvalue %struct.test %0, 1
44  %3 = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(
45    <vscale x 1 x double> poison,
46    <vscale x 1 x double> %1,
47    <vscale x 1 x double> %2, i64 7, i64 %vl)
48  ret <vscale x 1 x double> %3
49}
50
51declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(
52  <vscale x 1 x double>,
53  <vscale x 1 x double>,
54  <vscale x 1 x double>,
55  i64, i64)
56