xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll (revision a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64ZKSH
4
5declare i32 @llvm.riscv.sm3p0(i32);
6
7define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
8; RV64ZKSH-LABEL: sm3p0_i32:
9; RV64ZKSH:       # %bb.0:
10; RV64ZKSH-NEXT:    sm3p0 a0, a0
11; RV64ZKSH-NEXT:    ret
12  %val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
13  ret i32 %val
14}
15
16declare i32 @llvm.riscv.sm3p1(i32);
17
18define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
19; RV64ZKSH-LABEL: sm3p1_i32:
20; RV64ZKSH:       # %bb.0:
21; RV64ZKSH-NEXT:    sm3p1 a0, a0
22; RV64ZKSH-NEXT:    ret
23  %val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
24  ret i32 %val
25}
26