xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll (revision a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+zknh -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64ZKNH
4
5
6declare i32 @llvm.riscv.sha256sig0(i32);
7
8define signext i32 @sha256sig0_i32(i32 signext %a) nounwind {
9; RV64ZKNH-LABEL: sha256sig0_i32:
10; RV64ZKNH:       # %bb.0:
11; RV64ZKNH-NEXT:    sha256sig0 a0, a0
12; RV64ZKNH-NEXT:    ret
13    %val = call i32 @llvm.riscv.sha256sig0(i32 signext %a)
14    ret i32 %val
15}
16
17declare i32 @llvm.riscv.sha256sig1(i32);
18
19define signext i32 @sha256sig1_i32(i32 signext %a) nounwind {
20; RV64ZKNH-LABEL: sha256sig1_i32:
21; RV64ZKNH:       # %bb.0:
22; RV64ZKNH-NEXT:    sha256sig1 a0, a0
23; RV64ZKNH-NEXT:    ret
24    %val = call i32 @llvm.riscv.sha256sig1(i32 signext %a)
25    ret i32 %val
26}
27
28declare i32 @llvm.riscv.sha256sum0(i32);
29
30define signext i32 @sha256sum0_i32(i32 signext %a) nounwind {
31; RV64ZKNH-LABEL: sha256sum0_i32:
32; RV64ZKNH:       # %bb.0:
33; RV64ZKNH-NEXT:    sha256sum0 a0, a0
34; RV64ZKNH-NEXT:    ret
35    %val = call i32 @llvm.riscv.sha256sum0(i32 signext %a)
36    ret i32 %val
37}
38
39declare i32 @llvm.riscv.sha256sum1(i32);
40
41define signext i32 @sha256sum1_i32(i32 signext %a) nounwind {
42; RV64ZKNH-LABEL: sha256sum1_i32:
43; RV64ZKNH:       # %bb.0:
44; RV64ZKNH-NEXT:    sha256sum1 a0, a0
45; RV64ZKNH-NEXT:    ret
46    %val = call i32 @llvm.riscv.sha256sum1(i32 signext %a)
47    ret i32 %val
48}
49
50declare i64 @llvm.riscv.sha512sig0(i64);
51
52define i64 @sha512sig0(i64 %a) nounwind {
53; RV64ZKNH-LABEL: sha512sig0:
54; RV64ZKNH:       # %bb.0:
55; RV64ZKNH-NEXT:    sha512sig0 a0, a0
56; RV64ZKNH-NEXT:    ret
57    %val = call i64 @llvm.riscv.sha512sig0(i64 %a)
58    ret i64 %val
59}
60
61declare i64 @llvm.riscv.sha512sig1(i64);
62
63define i64 @sha512sig1(i64 %a) nounwind {
64; RV64ZKNH-LABEL: sha512sig1:
65; RV64ZKNH:       # %bb.0:
66; RV64ZKNH-NEXT:    sha512sig1 a0, a0
67; RV64ZKNH-NEXT:    ret
68    %val = call i64 @llvm.riscv.sha512sig1(i64 %a)
69    ret i64 %val
70}
71
72declare i64 @llvm.riscv.sha512sum0(i64);
73
74define i64 @sha512sum0(i64 %a) nounwind {
75; RV64ZKNH-LABEL: sha512sum0:
76; RV64ZKNH:       # %bb.0:
77; RV64ZKNH-NEXT:    sha512sum0 a0, a0
78; RV64ZKNH-NEXT:    ret
79    %val = call i64 @llvm.riscv.sha512sum0(i64 %a)
80    ret i64 %val
81}
82
83declare i64 @llvm.riscv.sha512sum1(i64);
84
85define i64 @sha512sum1(i64 %a) nounwind {
86; RV64ZKNH-LABEL: sha512sum1:
87; RV64ZKNH:       # %bb.0:
88; RV64ZKNH-NEXT:    sha512sum1 a0, a0
89; RV64ZKNH-NEXT:    ret
90    %val = call i64 @llvm.riscv.sha512sum1(i64 %a)
91    ret i64 %val
92}
93