xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll (revision 2ce0a5c8c383f2514c4fb10858d0e8607d5f21b4)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+zknd -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64ZKND
4
5declare i64 @llvm.riscv.aes64ds(i64, i64);
6
7define i64 @aes64ds(i64 %a, i64 %b) nounwind {
8; RV64ZKND-LABEL: aes64ds:
9; RV64ZKND:       # %bb.0:
10; RV64ZKND-NEXT:    aes64ds a0, a0, a1
11; RV64ZKND-NEXT:    ret
12    %val = call i64 @llvm.riscv.aes64ds(i64 %a, i64 %b)
13    ret i64 %val
14}
15
16declare i64 @llvm.riscv.aes64dsm(i64, i64);
17
18define i64 @aes64dsm(i64 %a, i64 %b) nounwind {
19; RV64ZKND-LABEL: aes64dsm:
20; RV64ZKND:       # %bb.0:
21; RV64ZKND-NEXT:    aes64dsm a0, a0, a1
22; RV64ZKND-NEXT:    ret
23    %val = call i64 @llvm.riscv.aes64dsm(i64 %a, i64 %b)
24    ret i64 %val
25}
26
27declare i64 @llvm.riscv.aes64im(i64);
28
29define i64 @aes64im(i64 %a) nounwind {
30; RV64ZKND-LABEL: aes64im:
31; RV64ZKND:       # %bb.0:
32; RV64ZKND-NEXT:    aes64im a0, a0
33; RV64ZKND-NEXT:    ret
34    %val = call i64 @llvm.riscv.aes64im(i64 %a)
35    ret i64 %val
36}
37