1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv64 -mattr=+zfhmin \ 3; RUN: -verify-machineinstrs -target-abi lp64f | \ 4; RUN: FileCheck -check-prefix=CHECKIZFHMIN %s 5; RUN: llc < %s -mtriple=riscv64 -mattr=+d \ 6; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \ 7; RUN: FileCheck -check-prefix=CHECKIZFHMIN %s 8; RUN: llc < %s -mtriple=riscv64 -mattr=+zhinxmin \ 9; RUN: -verify-machineinstrs -target-abi lp64 | \ 10; RUN: FileCheck -check-prefix=CHECKIZHINXMIN %s 11; RUN: llc < %s -mtriple=riscv64 -mattr=+zdinx \ 12; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \ 13; RUN: FileCheck -check-prefix=CHECKIZHINXMIN %s 14 15; These intrinsics require half and i64 to be legal types. 16 17declare i64 @llvm.llrint.i64.f16(half) 18 19define i64 @llrint_f16(half %a) nounwind { 20; CHECKIZFHMIN-LABEL: llrint_f16: 21; CHECKIZFHMIN: # %bb.0: 22; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 23; CHECKIZFHMIN-NEXT: fcvt.l.s a0, fa5 24; CHECKIZFHMIN-NEXT: ret 25; 26; CHECKIZHINXMIN-LABEL: llrint_f16: 27; CHECKIZHINXMIN: # %bb.0: 28; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 29; CHECKIZHINXMIN-NEXT: fcvt.l.s a0, a0 30; CHECKIZHINXMIN-NEXT: ret 31 %1 = call i64 @llvm.llrint.i64.f16(half %a) 32 ret i64 %1 33} 34 35declare i64 @llvm.llround.i64.f16(half) 36 37define i64 @llround_f16(half %a) nounwind { 38; CHECKIZFHMIN-LABEL: llround_f16: 39; CHECKIZFHMIN: # %bb.0: 40; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 41; CHECKIZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm 42; CHECKIZFHMIN-NEXT: ret 43; 44; CHECKIZHINXMIN-LABEL: llround_f16: 45; CHECKIZHINXMIN: # %bb.0: 46; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 47; CHECKIZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm 48; CHECKIZHINXMIN-NEXT: ret 49 %1 = call i64 @llvm.llround.i64.f16(half %a) 50 ret i64 %1 51} 52