1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ 3; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFHMIN 4; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ 5; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINXMIN 6 7; This file exhaustively checks half<->i32 conversions. 8 9define i32 @aext_fptosi(half %a) nounwind { 10; RV64IZFHMIN-LABEL: aext_fptosi: 11; RV64IZFHMIN: # %bb.0: 12; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 13; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 14; RV64IZFHMIN-NEXT: ret 15; 16; RV64IZHINXMIN-LABEL: aext_fptosi: 17; RV64IZHINXMIN: # %bb.0: 18; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 19; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz 20; RV64IZHINXMIN-NEXT: ret 21 %1 = fptosi half %a to i32 22 ret i32 %1 23} 24 25define signext i32 @sext_fptosi(half %a) nounwind { 26; RV64IZFHMIN-LABEL: sext_fptosi: 27; RV64IZFHMIN: # %bb.0: 28; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 29; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 30; RV64IZFHMIN-NEXT: ret 31; 32; RV64IZHINXMIN-LABEL: sext_fptosi: 33; RV64IZHINXMIN: # %bb.0: 34; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 35; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz 36; RV64IZHINXMIN-NEXT: ret 37 %1 = fptosi half %a to i32 38 ret i32 %1 39} 40 41define zeroext i32 @zext_fptosi(half %a) nounwind { 42; RV64IZFHMIN-LABEL: zext_fptosi: 43; RV64IZFHMIN: # %bb.0: 44; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 45; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz 46; RV64IZFHMIN-NEXT: slli a0, a0, 32 47; RV64IZFHMIN-NEXT: srli a0, a0, 32 48; RV64IZFHMIN-NEXT: ret 49; 50; RV64IZHINXMIN-LABEL: zext_fptosi: 51; RV64IZHINXMIN: # %bb.0: 52; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 53; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz 54; RV64IZHINXMIN-NEXT: slli a0, a0, 32 55; RV64IZHINXMIN-NEXT: srli a0, a0, 32 56; RV64IZHINXMIN-NEXT: ret 57 %1 = fptosi half %a to i32 58 ret i32 %1 59} 60 61define i32 @aext_fptoui(half %a) nounwind { 62; RV64IZFHMIN-LABEL: aext_fptoui: 63; RV64IZFHMIN: # %bb.0: 64; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 65; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 66; RV64IZFHMIN-NEXT: ret 67; 68; RV64IZHINXMIN-LABEL: aext_fptoui: 69; RV64IZHINXMIN: # %bb.0: 70; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 71; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz 72; RV64IZHINXMIN-NEXT: ret 73 %1 = fptoui half %a to i32 74 ret i32 %1 75} 76 77define signext i32 @sext_fptoui(half %a) nounwind { 78; RV64IZFHMIN-LABEL: sext_fptoui: 79; RV64IZFHMIN: # %bb.0: 80; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 81; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz 82; RV64IZFHMIN-NEXT: ret 83; 84; RV64IZHINXMIN-LABEL: sext_fptoui: 85; RV64IZHINXMIN: # %bb.0: 86; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 87; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz 88; RV64IZHINXMIN-NEXT: ret 89 %1 = fptoui half %a to i32 90 ret i32 %1 91} 92 93define zeroext i32 @zext_fptoui(half %a) nounwind { 94; RV64IZFHMIN-LABEL: zext_fptoui: 95; RV64IZFHMIN: # %bb.0: 96; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 97; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz 98; RV64IZFHMIN-NEXT: ret 99; 100; RV64IZHINXMIN-LABEL: zext_fptoui: 101; RV64IZHINXMIN: # %bb.0: 102; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 103; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz 104; RV64IZHINXMIN-NEXT: ret 105 %1 = fptoui half %a to i32 106 ret i32 %1 107} 108 109define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind { 110; RV64IZFHMIN-LABEL: bcvt_f16_to_aext_i16: 111; RV64IZFHMIN: # %bb.0: 112; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 113; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 114; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5 115; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 116; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5 117; RV64IZFHMIN-NEXT: ret 118; 119; RV64IZHINXMIN-LABEL: bcvt_f16_to_aext_i16: 120; RV64IZHINXMIN: # %bb.0: 121; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 122; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 123; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1 124; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 125; RV64IZHINXMIN-NEXT: ret 126 %1 = fadd half %a, %b 127 %2 = bitcast half %1 to i16 128 ret i16 %2 129} 130 131define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind { 132; RV64IZFHMIN-LABEL: bcvt_f16_to_sext_i16: 133; RV64IZFHMIN: # %bb.0: 134; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 135; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 136; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5 137; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 138; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5 139; RV64IZFHMIN-NEXT: ret 140; 141; RV64IZHINXMIN-LABEL: bcvt_f16_to_sext_i16: 142; RV64IZHINXMIN: # %bb.0: 143; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 144; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 145; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1 146; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 147; RV64IZHINXMIN-NEXT: slli a0, a0, 48 148; RV64IZHINXMIN-NEXT: srai a0, a0, 48 149; RV64IZHINXMIN-NEXT: ret 150 %1 = fadd half %a, %b 151 %2 = bitcast half %1 to i16 152 ret i16 %2 153} 154 155define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind { 156; RV64IZFHMIN-LABEL: bcvt_f16_to_zext_i16: 157; RV64IZFHMIN: # %bb.0: 158; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1 159; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0 160; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5 161; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5 162; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5 163; RV64IZFHMIN-NEXT: slli a0, a0, 48 164; RV64IZFHMIN-NEXT: srli a0, a0, 48 165; RV64IZFHMIN-NEXT: ret 166; 167; RV64IZHINXMIN-LABEL: bcvt_f16_to_zext_i16: 168; RV64IZHINXMIN: # %bb.0: 169; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 170; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 171; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1 172; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 173; RV64IZHINXMIN-NEXT: slli a0, a0, 48 174; RV64IZHINXMIN-NEXT: srli a0, a0, 48 175; RV64IZHINXMIN-NEXT: ret 176 %1 = fadd half %a, %b 177 %2 = bitcast half %1 to i16 178 ret i16 %2 179} 180 181define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind { 182; RV64IZFHMIN-LABEL: bcvt_i64_to_f16_via_i16: 183; RV64IZFHMIN: # %bb.0: 184; RV64IZFHMIN-NEXT: fmv.h.x fa5, a0 185; RV64IZFHMIN-NEXT: fmv.h.x fa4, a1 186; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4 187; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 188; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4 189; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 190; RV64IZFHMIN-NEXT: ret 191; 192; RV64IZHINXMIN-LABEL: bcvt_i64_to_f16_via_i16: 193; RV64IZHINXMIN: # %bb.0: 194; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1 195; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 196; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1 197; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 198; RV64IZHINXMIN-NEXT: ret 199 %1 = trunc i64 %a to i16 200 %2 = trunc i64 %b to i16 201 %3 = bitcast i16 %1 to half 202 %4 = bitcast i16 %2 to half 203 %5 = fadd half %3, %4 204 ret half %5 205} 206 207define half @uitofp_aext_i32_to_f16(i32 %a) nounwind { 208; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16: 209; RV64IZFHMIN: # %bb.0: 210; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0 211; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 212; RV64IZFHMIN-NEXT: ret 213; 214; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16: 215; RV64IZHINXMIN: # %bb.0: 216; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0 217; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 218; RV64IZHINXMIN-NEXT: ret 219 %1 = uitofp i32 %a to half 220 ret half %1 221} 222 223define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind { 224; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16: 225; RV64IZFHMIN: # %bb.0: 226; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0 227; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 228; RV64IZFHMIN-NEXT: ret 229; 230; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16: 231; RV64IZHINXMIN: # %bb.0: 232; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0 233; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 234; RV64IZHINXMIN-NEXT: ret 235 %1 = uitofp i32 %a to half 236 ret half %1 237} 238 239define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind { 240; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16: 241; RV64IZFHMIN: # %bb.0: 242; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0 243; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 244; RV64IZFHMIN-NEXT: ret 245; 246; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16: 247; RV64IZHINXMIN: # %bb.0: 248; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0 249; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 250; RV64IZHINXMIN-NEXT: ret 251 %1 = uitofp i32 %a to half 252 ret half %1 253} 254 255define half @sitofp_aext_i32_to_f16(i32 %a) nounwind { 256; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16: 257; RV64IZFHMIN: # %bb.0: 258; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0 259; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 260; RV64IZFHMIN-NEXT: ret 261; 262; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16: 263; RV64IZHINXMIN: # %bb.0: 264; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0 265; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 266; RV64IZHINXMIN-NEXT: ret 267 %1 = sitofp i32 %a to half 268 ret half %1 269} 270 271define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind { 272; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16: 273; RV64IZFHMIN: # %bb.0: 274; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0 275; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 276; RV64IZFHMIN-NEXT: ret 277; 278; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16: 279; RV64IZHINXMIN: # %bb.0: 280; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0 281; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 282; RV64IZHINXMIN-NEXT: ret 283 %1 = sitofp i32 %a to half 284 ret half %1 285} 286 287define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind { 288; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16: 289; RV64IZFHMIN: # %bb.0: 290; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0 291; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5 292; RV64IZFHMIN-NEXT: ret 293; 294; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16: 295; RV64IZHINXMIN: # %bb.0: 296; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0 297; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0 298; RV64IZHINXMIN-NEXT: ret 299 %1 = sitofp i32 %a to half 300 ret half %1 301} 302