1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv64 -mattr=+zfh \ 3; RUN: -verify-machineinstrs -target-abi lp64f | \ 4; RUN: FileCheck -check-prefix=RV64IZFH %s 5; RUN: llc < %s -mtriple=riscv64 -mattr=+d \ 6; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \ 7; RUN: FileCheck -check-prefix=RV64IDZFH %s 8; RUN: llc < %s -mtriple=riscv64 -mattr=+zhinx \ 9; RUN: -verify-machineinstrs -target-abi lp64 | \ 10; RUN: FileCheck -check-prefix=RV64IZHINX %s 11; RUN: llc < %s -mtriple=riscv64 -mattr=+zdinx \ 12; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \ 13; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s 14 15; These intrinsics require half and i64 to be legal types. 16 17declare i64 @llvm.llrint.i64.f16(half) 18 19define i64 @llrint_f16(half %a) nounwind { 20; RV64IZFH-LABEL: llrint_f16: 21; RV64IZFH: # %bb.0: 22; RV64IZFH-NEXT: fcvt.l.h a0, fa0 23; RV64IZFH-NEXT: ret 24; 25; RV64IDZFH-LABEL: llrint_f16: 26; RV64IDZFH: # %bb.0: 27; RV64IDZFH-NEXT: fcvt.l.h a0, fa0 28; RV64IDZFH-NEXT: ret 29; 30; RV64IZHINX-LABEL: llrint_f16: 31; RV64IZHINX: # %bb.0: 32; RV64IZHINX-NEXT: fcvt.l.h a0, a0 33; RV64IZHINX-NEXT: ret 34; 35; RV64IZDINXZHINX-LABEL: llrint_f16: 36; RV64IZDINXZHINX: # %bb.0: 37; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0 38; RV64IZDINXZHINX-NEXT: ret 39 %1 = call i64 @llvm.llrint.i64.f16(half %a) 40 ret i64 %1 41} 42 43declare i64 @llvm.llround.i64.f16(half) 44 45define i64 @llround_f16(half %a) nounwind { 46; RV64IZFH-LABEL: llround_f16: 47; RV64IZFH: # %bb.0: 48; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm 49; RV64IZFH-NEXT: ret 50; 51; RV64IDZFH-LABEL: llround_f16: 52; RV64IDZFH: # %bb.0: 53; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm 54; RV64IDZFH-NEXT: ret 55; 56; RV64IZHINX-LABEL: llround_f16: 57; RV64IZHINX: # %bb.0: 58; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm 59; RV64IZHINX-NEXT: ret 60; 61; RV64IZDINXZHINX-LABEL: llround_f16: 62; RV64IZDINXZHINX: # %bb.0: 63; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm 64; RV64IZDINXZHINX-NEXT: ret 65 %1 = call i64 @llvm.llround.i64.f16(half %a) 66 ret i64 %1 67} 68