1615d71d9SWu Xinlong; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2615d71d9SWu Xinlong; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \ 3615d71d9SWu Xinlong; RUN: | FileCheck %s -check-prefix=RV64ZBKB 4615d71d9SWu Xinlong 5*be253cb9SCraig Topperdeclare i64 @llvm.riscv.brev8.i64(i64) 6615d71d9SWu Xinlong 7615d71d9SWu Xinlongdefine i64 @brev8(i64 %a) nounwind { 8615d71d9SWu Xinlong; RV64ZBKB-LABEL: brev8: 9615d71d9SWu Xinlong; RV64ZBKB: # %bb.0: 10615d71d9SWu Xinlong; RV64ZBKB-NEXT: brev8 a0, a0 11615d71d9SWu Xinlong; RV64ZBKB-NEXT: ret 12*be253cb9SCraig Topper %val = call i64 @llvm.riscv.brev8.i64(i64 %a) 13615d71d9SWu Xinlong ret i64 %val 14615d71d9SWu Xinlong} 15615d71d9SWu Xinlong 16e1075186SCraig Topper; Test that rev8 is recognized as preserving zero extension. 17e1075186SCraig Topperdefine zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind { 18e1075186SCraig Topper; RV64ZBKB-LABEL: brev8_knownbits: 19e1075186SCraig Topper; RV64ZBKB: # %bb.0: 20e1075186SCraig Topper; RV64ZBKB-NEXT: brev8 a0, a0 21e1075186SCraig Topper; RV64ZBKB-NEXT: ret 22e1075186SCraig Topper %zext = zext i16 %a to i64 23*be253cb9SCraig Topper %val = call i64 @llvm.riscv.brev8.i64(i64 %zext) 24e1075186SCraig Topper %trunc = trunc i64 %val to i16 25e1075186SCraig Topper ret i16 %trunc 26e1075186SCraig Topper} 27e1075186SCraig Topper 28615d71d9SWu Xinlongdeclare i64 @llvm.bswap.i64(i64) 29615d71d9SWu Xinlong 30615d71d9SWu Xinlongdefine i64 @rev8_i64(i64 %a) { 31615d71d9SWu Xinlong; RV64ZBKB-LABEL: rev8_i64: 32615d71d9SWu Xinlong; RV64ZBKB: # %bb.0: 33615d71d9SWu Xinlong; RV64ZBKB-NEXT: rev8 a0, a0 34615d71d9SWu Xinlong; RV64ZBKB-NEXT: ret 35615d71d9SWu Xinlong %1 = call i64 @llvm.bswap.i64(i64 %a) 36615d71d9SWu Xinlong ret i64 %1 37615d71d9SWu Xinlong} 38*be253cb9SCraig Topper 39*be253cb9SCraig Topperdeclare i32 @llvm.riscv.brev8.i32(i32) 40*be253cb9SCraig Topper 41*be253cb9SCraig Topperdefine signext i32 @brev8_i32(i32 signext %a) nounwind { 42*be253cb9SCraig Topper; RV64ZBKB-LABEL: brev8_i32: 43*be253cb9SCraig Topper; RV64ZBKB: # %bb.0: 44*be253cb9SCraig Topper; RV64ZBKB-NEXT: brev8 a0, a0 45*be253cb9SCraig Topper; RV64ZBKB-NEXT: sext.w a0, a0 46*be253cb9SCraig Topper; RV64ZBKB-NEXT: ret 47*be253cb9SCraig Topper %val = call i32 @llvm.riscv.brev8.i32(i32 %a) 48*be253cb9SCraig Topper ret i32 %val 49*be253cb9SCraig Topper} 50*be253cb9SCraig Topper 51*be253cb9SCraig Topper; Test that rev8 is recognized as preserving zero extension. 52*be253cb9SCraig Topperdefine zeroext i16 @brev8_i32_knownbits(i16 zeroext %a) nounwind { 53*be253cb9SCraig Topper; RV64ZBKB-LABEL: brev8_i32_knownbits: 54*be253cb9SCraig Topper; RV64ZBKB: # %bb.0: 55*be253cb9SCraig Topper; RV64ZBKB-NEXT: brev8 a0, a0 56*be253cb9SCraig Topper; RV64ZBKB-NEXT: ret 57*be253cb9SCraig Topper %zext = zext i16 %a to i32 58*be253cb9SCraig Topper %val = call i32 @llvm.riscv.brev8.i32(i32 %zext) 59*be253cb9SCraig Topper %trunc = trunc i32 %val to i16 60*be253cb9SCraig Topper ret i16 %trunc 61*be253cb9SCraig Topper} 62*be253cb9SCraig Topper 63*be253cb9SCraig Topperdeclare i32 @llvm.bswap.i32(i32) 64*be253cb9SCraig Topper 65*be253cb9SCraig Topperdefine signext i32 @rev8_i32(i32 signext %a) { 66*be253cb9SCraig Topper; RV64ZBKB-LABEL: rev8_i32: 67*be253cb9SCraig Topper; RV64ZBKB: # %bb.0: 68*be253cb9SCraig Topper; RV64ZBKB-NEXT: rev8 a0, a0 69*be253cb9SCraig Topper; RV64ZBKB-NEXT: srai a0, a0, 32 70*be253cb9SCraig Topper; RV64ZBKB-NEXT: ret 71*be253cb9SCraig Topper %1 = call i32 @llvm.bswap.i32(i32 %a) 72*be253cb9SCraig Topper ret i32 %1 73*be253cb9SCraig Topper} 74