xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll (revision be253cb987a9fa078c66038d2325f81eeacf7209) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64ZBKB
4
5declare i64 @llvm.riscv.brev8.i64(i64)
6
7define i64 @brev8(i64 %a) nounwind {
8; RV64ZBKB-LABEL: brev8:
9; RV64ZBKB:       # %bb.0:
10; RV64ZBKB-NEXT:    brev8 a0, a0
11; RV64ZBKB-NEXT:    ret
12  %val = call i64 @llvm.riscv.brev8.i64(i64 %a)
13  ret i64 %val
14}
15
16; Test that rev8 is recognized as preserving zero extension.
17define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
18; RV64ZBKB-LABEL: brev8_knownbits:
19; RV64ZBKB:       # %bb.0:
20; RV64ZBKB-NEXT:    brev8 a0, a0
21; RV64ZBKB-NEXT:    ret
22  %zext = zext i16 %a to i64
23  %val = call i64 @llvm.riscv.brev8.i64(i64 %zext)
24  %trunc = trunc i64 %val to i16
25  ret i16 %trunc
26}
27
28declare i64 @llvm.bswap.i64(i64)
29
30define i64 @rev8_i64(i64 %a) {
31; RV64ZBKB-LABEL: rev8_i64:
32; RV64ZBKB:       # %bb.0:
33; RV64ZBKB-NEXT:    rev8 a0, a0
34; RV64ZBKB-NEXT:    ret
35  %1 = call i64 @llvm.bswap.i64(i64 %a)
36  ret i64 %1
37}
38
39declare i32 @llvm.riscv.brev8.i32(i32)
40
41define signext i32 @brev8_i32(i32 signext %a) nounwind {
42; RV64ZBKB-LABEL: brev8_i32:
43; RV64ZBKB:       # %bb.0:
44; RV64ZBKB-NEXT:    brev8 a0, a0
45; RV64ZBKB-NEXT:    sext.w a0, a0
46; RV64ZBKB-NEXT:    ret
47  %val = call i32 @llvm.riscv.brev8.i32(i32 %a)
48  ret i32 %val
49}
50
51; Test that rev8 is recognized as preserving zero extension.
52define zeroext i16 @brev8_i32_knownbits(i16 zeroext %a) nounwind {
53; RV64ZBKB-LABEL: brev8_i32_knownbits:
54; RV64ZBKB:       # %bb.0:
55; RV64ZBKB-NEXT:    brev8 a0, a0
56; RV64ZBKB-NEXT:    ret
57  %zext = zext i16 %a to i32
58  %val = call i32 @llvm.riscv.brev8.i32(i32 %zext)
59  %trunc = trunc i32 %val to i16
60  ret i16 %trunc
61}
62
63declare i32 @llvm.bswap.i32(i32)
64
65define signext i32 @rev8_i32(i32 signext %a) {
66; RV64ZBKB-LABEL: rev8_i32:
67; RV64ZBKB:       # %bb.0:
68; RV64ZBKB-NEXT:    rev8 a0, a0
69; RV64ZBKB-NEXT:    srai a0, a0, 32
70; RV64ZBKB-NEXT:    ret
71  %1 = call i32 @llvm.bswap.i32(i32 %a)
72  ret i32 %1
73}
74