xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll (revision ea3683e98f107622ce54fa3d4c1457f4d597f808) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64ZBC-ZBKC
4; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64ZBC-ZBKC
6
7declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
8
9define i64 @clmul64(i64 %a, i64 %b) nounwind {
10; RV64ZBC-ZBKC-LABEL: clmul64:
11; RV64ZBC-ZBKC:       # %bb.0:
12; RV64ZBC-ZBKC-NEXT:    clmul a0, a0, a1
13; RV64ZBC-ZBKC-NEXT:    ret
14  %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
15  ret i64 %tmp
16}
17
18declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
19
20define i64 @clmul64h(i64 %a, i64 %b) nounwind {
21; RV64ZBC-ZBKC-LABEL: clmul64h:
22; RV64ZBC-ZBKC:       # %bb.0:
23; RV64ZBC-ZBKC-NEXT:    clmulh a0, a0, a1
24; RV64ZBC-ZBKC-NEXT:    ret
25  %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
26  ret i64 %tmp
27}
28
29declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
30
31define signext i32 @clmul32(i32 signext %a, i32 signext %b) nounwind {
32; RV64ZBC-ZBKC-LABEL: clmul32:
33; RV64ZBC-ZBKC:       # %bb.0:
34; RV64ZBC-ZBKC-NEXT:    clmul a0, a0, a1
35; RV64ZBC-ZBKC-NEXT:    sext.w a0, a0
36; RV64ZBC-ZBKC-NEXT:    ret
37  %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
38  ret i32 %tmp
39}
40
41declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
42
43define signext i32 @clmul32h(i32 signext %a, i32 signext %b) nounwind {
44; RV64ZBC-ZBKC-LABEL: clmul32h:
45; RV64ZBC-ZBKC:       # %bb.0:
46; RV64ZBC-ZBKC-NEXT:    slli a1, a1, 32
47; RV64ZBC-ZBKC-NEXT:    slli a0, a0, 32
48; RV64ZBC-ZBKC-NEXT:    clmulh a0, a0, a1
49; RV64ZBC-ZBKC-NEXT:    srai a0, a0, 32
50; RV64ZBC-ZBKC-NEXT:    ret
51  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
52  ret i32 %tmp
53}
54
55; FIXME: We could avoid the slli instructions by using clmul+srai since the
56; inputs are zero extended.
57define signext i32 @clmul32h_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
58; RV64ZBC-ZBKC-LABEL: clmul32h_zext:
59; RV64ZBC-ZBKC:       # %bb.0:
60; RV64ZBC-ZBKC-NEXT:    slli a1, a1, 32
61; RV64ZBC-ZBKC-NEXT:    slli a0, a0, 32
62; RV64ZBC-ZBKC-NEXT:    clmulh a0, a0, a1
63; RV64ZBC-ZBKC-NEXT:    srai a0, a0, 32
64; RV64ZBC-ZBKC-NEXT:    ret
65  %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
66  ret i32 %tmp
67}
68