1f78d932cSLevy Hsu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 233d008b1SAlex Bradbury; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \ 3e3560270SCraig Topper; RUN: | FileCheck %s -check-prefix=RV64ZBC 4f78d932cSLevy Hsu 5f78d932cSLevy Hsudeclare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) 6f78d932cSLevy Hsu 7f78d932cSLevy Hsudefine i64 @clmul64r(i64 %a, i64 %b) nounwind { 8e3560270SCraig Topper; RV64ZBC-LABEL: clmul64r: 9e3560270SCraig Topper; RV64ZBC: # %bb.0: 10e3560270SCraig Topper; RV64ZBC-NEXT: clmulr a0, a0, a1 11e3560270SCraig Topper; RV64ZBC-NEXT: ret 12f78d932cSLevy Hsu %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) 13f78d932cSLevy Hsu ret i64 %tmp 14f78d932cSLevy Hsu} 153a0a25f9SCraig Topper 163a0a25f9SCraig Topperdeclare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 173a0a25f9SCraig Topper 183a0a25f9SCraig Topperdefine signext i32 @clmul32r(i32 signext %a, i32 signext %b) nounwind { 193a0a25f9SCraig Topper; RV64ZBC-LABEL: clmul32r: 203a0a25f9SCraig Topper; RV64ZBC: # %bb.0: 213a0a25f9SCraig Topper; RV64ZBC-NEXT: slli a1, a1, 32 223a0a25f9SCraig Topper; RV64ZBC-NEXT: slli a0, a0, 32 23*ea3683e9SCraig Topper; RV64ZBC-NEXT: clmulr a0, a0, a1 24*ea3683e9SCraig Topper; RV64ZBC-NEXT: srai a0, a0, 32 25*ea3683e9SCraig Topper; RV64ZBC-NEXT: ret 26*ea3683e9SCraig Topper %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 27*ea3683e9SCraig Topper ret i32 %tmp 28*ea3683e9SCraig Topper} 29*ea3683e9SCraig Topper 30*ea3683e9SCraig Topper; FIXME: We could avoid the slli instructions by using clmul+srli+sext.w since 31*ea3683e9SCraig Topper; the inputs are zero extended. 32*ea3683e9SCraig Topperdefine signext i32 @clmul32r_zext(i32 zeroext %a, i32 zeroext %b) nounwind { 33*ea3683e9SCraig Topper; RV64ZBC-LABEL: clmul32r_zext: 34*ea3683e9SCraig Topper; RV64ZBC: # %bb.0: 35*ea3683e9SCraig Topper; RV64ZBC-NEXT: slli a1, a1, 32 36*ea3683e9SCraig Topper; RV64ZBC-NEXT: slli a0, a0, 32 37*ea3683e9SCraig Topper; RV64ZBC-NEXT: clmulr a0, a0, a1 38*ea3683e9SCraig Topper; RV64ZBC-NEXT: srai a0, a0, 32 393a0a25f9SCraig Topper; RV64ZBC-NEXT: ret 403a0a25f9SCraig Topper %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 413a0a25f9SCraig Topper ret i32 %tmp 423a0a25f9SCraig Topper} 43