1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV64ZBC 4 5declare i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) 6 7define i64 @clmul64r(i64 %a, i64 %b) nounwind { 8; RV64ZBC-LABEL: clmul64r: 9; RV64ZBC: # %bb.0: 10; RV64ZBC-NEXT: clmulr a0, a0, a1 11; RV64ZBC-NEXT: ret 12 %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b) 13 ret i64 %tmp 14} 15 16declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 17 18define signext i32 @clmul32r(i32 signext %a, i32 signext %b) nounwind { 19; RV64ZBC-LABEL: clmul32r: 20; RV64ZBC: # %bb.0: 21; RV64ZBC-NEXT: slli a1, a1, 32 22; RV64ZBC-NEXT: slli a0, a0, 32 23; RV64ZBC-NEXT: clmulr a0, a0, a1 24; RV64ZBC-NEXT: srai a0, a0, 32 25; RV64ZBC-NEXT: ret 26 %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 27 ret i32 %tmp 28} 29 30; FIXME: We could avoid the slli instructions by using clmul+srli+sext.w since 31; the inputs are zero extended. 32define signext i32 @clmul32r_zext(i32 zeroext %a, i32 zeroext %b) nounwind { 33; RV64ZBC-LABEL: clmul32r_zext: 34; RV64ZBC: # %bb.0: 35; RV64ZBC-NEXT: slli a1, a1, 32 36; RV64ZBC-NEXT: slli a0, a0, 32 37; RV64ZBC-NEXT: clmulr a0, a0, a1 38; RV64ZBC-NEXT: srai a0, a0, 32 39; RV64ZBC-NEXT: ret 40 %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 41 ret i32 %tmp 42} 43