xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll (revision 862407510595e37266e3dc0df6a00cad78f420bf) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=RV64,RV64I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+zba < %s \
5; RUN:   | FileCheck %s -check-prefixes=RV64,RV64ZBA
6
7; The patterns for the 'W' suffixed RV64I instructions have the potential of
8; missing cases. This file checks all the variants of
9; sign-extended/zero-extended/any-extended inputs and outputs.
10
11; The 64-bit add instruction can safely be used when the result is anyext.
12
13define i32 @aext_addw_aext_aext(i32 %a, i32 %b) nounwind {
14; RV64-LABEL: aext_addw_aext_aext:
15; RV64:       # %bb.0:
16; RV64-NEXT:    addw a0, a0, a1
17; RV64-NEXT:    ret
18  %1 = add i32 %a, %b
19  ret i32 %1
20}
21
22define i32 @aext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
23; RV64-LABEL: aext_addw_aext_sext:
24; RV64:       # %bb.0:
25; RV64-NEXT:    addw a0, a0, a1
26; RV64-NEXT:    ret
27  %1 = add i32 %a, %b
28  ret i32 %1
29}
30
31define i32 @aext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
32; RV64-LABEL: aext_addw_aext_zext:
33; RV64:       # %bb.0:
34; RV64-NEXT:    addw a0, a0, a1
35; RV64-NEXT:    ret
36  %1 = add i32 %a, %b
37  ret i32 %1
38}
39
40define i32 @aext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
41; RV64-LABEL: aext_addw_sext_aext:
42; RV64:       # %bb.0:
43; RV64-NEXT:    addw a0, a0, a1
44; RV64-NEXT:    ret
45  %1 = add i32 %a, %b
46  ret i32 %1
47}
48
49define i32 @aext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
50; RV64-LABEL: aext_addw_sext_sext:
51; RV64:       # %bb.0:
52; RV64-NEXT:    addw a0, a0, a1
53; RV64-NEXT:    ret
54  %1 = add i32 %a, %b
55  ret i32 %1
56}
57
58define i32 @aext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
59; RV64-LABEL: aext_addw_sext_zext:
60; RV64:       # %bb.0:
61; RV64-NEXT:    addw a0, a0, a1
62; RV64-NEXT:    ret
63  %1 = add i32 %a, %b
64  ret i32 %1
65}
66
67define i32 @aext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
68; RV64-LABEL: aext_addw_zext_aext:
69; RV64:       # %bb.0:
70; RV64-NEXT:    addw a0, a0, a1
71; RV64-NEXT:    ret
72  %1 = add i32 %a, %b
73  ret i32 %1
74}
75
76define i32 @aext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
77; RV64-LABEL: aext_addw_zext_sext:
78; RV64:       # %bb.0:
79; RV64-NEXT:    addw a0, a0, a1
80; RV64-NEXT:    ret
81  %1 = add i32 %a, %b
82  ret i32 %1
83}
84
85define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
86; RV64-LABEL: aext_addw_zext_zext:
87; RV64:       # %bb.0:
88; RV64-NEXT:    addw a0, a0, a1
89; RV64-NEXT:    ret
90  %1 = add i32 %a, %b
91  ret i32 %1
92}
93
94; Always select addw when a signext result is required.
95
96define signext i32 @sext_addw_aext_aext(i32 %a, i32 %b) nounwind {
97; RV64-LABEL: sext_addw_aext_aext:
98; RV64:       # %bb.0:
99; RV64-NEXT:    addw a0, a0, a1
100; RV64-NEXT:    ret
101  %1 = add i32 %a, %b
102  ret i32 %1
103}
104
105define signext i32 @sext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
106; RV64-LABEL: sext_addw_aext_sext:
107; RV64:       # %bb.0:
108; RV64-NEXT:    addw a0, a0, a1
109; RV64-NEXT:    ret
110  %1 = add i32 %a, %b
111  ret i32 %1
112}
113
114define signext i32 @sext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
115; RV64-LABEL: sext_addw_aext_zext:
116; RV64:       # %bb.0:
117; RV64-NEXT:    addw a0, a0, a1
118; RV64-NEXT:    ret
119  %1 = add i32 %a, %b
120  ret i32 %1
121}
122
123define signext i32 @sext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
124; RV64-LABEL: sext_addw_sext_aext:
125; RV64:       # %bb.0:
126; RV64-NEXT:    addw a0, a0, a1
127; RV64-NEXT:    ret
128  %1 = add i32 %a, %b
129  ret i32 %1
130}
131
132define signext i32 @sext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
133; RV64-LABEL: sext_addw_sext_sext:
134; RV64:       # %bb.0:
135; RV64-NEXT:    addw a0, a0, a1
136; RV64-NEXT:    ret
137  %1 = add i32 %a, %b
138  ret i32 %1
139}
140
141define signext i32 @sext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
142; RV64-LABEL: sext_addw_sext_zext:
143; RV64:       # %bb.0:
144; RV64-NEXT:    addw a0, a0, a1
145; RV64-NEXT:    ret
146  %1 = add i32 %a, %b
147  ret i32 %1
148}
149
150define signext i32 @sext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
151; RV64-LABEL: sext_addw_zext_aext:
152; RV64:       # %bb.0:
153; RV64-NEXT:    addw a0, a0, a1
154; RV64-NEXT:    ret
155  %1 = add i32 %a, %b
156  ret i32 %1
157}
158
159define signext i32 @sext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
160; RV64-LABEL: sext_addw_zext_sext:
161; RV64:       # %bb.0:
162; RV64-NEXT:    addw a0, a0, a1
163; RV64-NEXT:    ret
164  %1 = add i32 %a, %b
165  ret i32 %1
166}
167
168define signext i32 @sext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
169; RV64-LABEL: sext_addw_zext_zext:
170; RV64:       # %bb.0:
171; RV64-NEXT:    addw a0, a0, a1
172; RV64-NEXT:    ret
173  %1 = add i32 %a, %b
174  ret i32 %1
175}
176
177; 64-bit add followed by zero-extension is a safe option when a zeroext result
178; is required.
179
180define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {
181; RV64I-LABEL: zext_addw_aext_aext:
182; RV64I:       # %bb.0:
183; RV64I-NEXT:    add a0, a0, a1
184; RV64I-NEXT:    slli a0, a0, 32
185; RV64I-NEXT:    srli a0, a0, 32
186; RV64I-NEXT:    ret
187;
188; RV64ZBA-LABEL: zext_addw_aext_aext:
189; RV64ZBA:       # %bb.0:
190; RV64ZBA-NEXT:    add a0, a0, a1
191; RV64ZBA-NEXT:    zext.w a0, a0
192; RV64ZBA-NEXT:    ret
193  %1 = add i32 %a, %b
194  ret i32 %1
195}
196
197define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
198; RV64I-LABEL: zext_addw_aext_sext:
199; RV64I:       # %bb.0:
200; RV64I-NEXT:    add a0, a0, a1
201; RV64I-NEXT:    slli a0, a0, 32
202; RV64I-NEXT:    srli a0, a0, 32
203; RV64I-NEXT:    ret
204;
205; RV64ZBA-LABEL: zext_addw_aext_sext:
206; RV64ZBA:       # %bb.0:
207; RV64ZBA-NEXT:    add a0, a0, a1
208; RV64ZBA-NEXT:    zext.w a0, a0
209; RV64ZBA-NEXT:    ret
210  %1 = add i32 %a, %b
211  ret i32 %1
212}
213
214define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
215; RV64I-LABEL: zext_addw_aext_zext:
216; RV64I:       # %bb.0:
217; RV64I-NEXT:    add a0, a0, a1
218; RV64I-NEXT:    slli a0, a0, 32
219; RV64I-NEXT:    srli a0, a0, 32
220; RV64I-NEXT:    ret
221;
222; RV64ZBA-LABEL: zext_addw_aext_zext:
223; RV64ZBA:       # %bb.0:
224; RV64ZBA-NEXT:    add a0, a0, a1
225; RV64ZBA-NEXT:    zext.w a0, a0
226; RV64ZBA-NEXT:    ret
227  %1 = add i32 %a, %b
228  ret i32 %1
229}
230
231define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
232; RV64I-LABEL: zext_addw_sext_aext:
233; RV64I:       # %bb.0:
234; RV64I-NEXT:    add a0, a0, a1
235; RV64I-NEXT:    slli a0, a0, 32
236; RV64I-NEXT:    srli a0, a0, 32
237; RV64I-NEXT:    ret
238;
239; RV64ZBA-LABEL: zext_addw_sext_aext:
240; RV64ZBA:       # %bb.0:
241; RV64ZBA-NEXT:    add a0, a0, a1
242; RV64ZBA-NEXT:    zext.w a0, a0
243; RV64ZBA-NEXT:    ret
244  %1 = add i32 %a, %b
245  ret i32 %1
246}
247
248define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
249; RV64I-LABEL: zext_addw_sext_sext:
250; RV64I:       # %bb.0:
251; RV64I-NEXT:    add a0, a0, a1
252; RV64I-NEXT:    slli a0, a0, 32
253; RV64I-NEXT:    srli a0, a0, 32
254; RV64I-NEXT:    ret
255;
256; RV64ZBA-LABEL: zext_addw_sext_sext:
257; RV64ZBA:       # %bb.0:
258; RV64ZBA-NEXT:    add a0, a0, a1
259; RV64ZBA-NEXT:    zext.w a0, a0
260; RV64ZBA-NEXT:    ret
261  %1 = add i32 %a, %b
262  ret i32 %1
263}
264
265define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
266; RV64I-LABEL: zext_addw_sext_zext:
267; RV64I:       # %bb.0:
268; RV64I-NEXT:    add a0, a0, a1
269; RV64I-NEXT:    slli a0, a0, 32
270; RV64I-NEXT:    srli a0, a0, 32
271; RV64I-NEXT:    ret
272;
273; RV64ZBA-LABEL: zext_addw_sext_zext:
274; RV64ZBA:       # %bb.0:
275; RV64ZBA-NEXT:    add a0, a0, a1
276; RV64ZBA-NEXT:    zext.w a0, a0
277; RV64ZBA-NEXT:    ret
278  %1 = add i32 %a, %b
279  ret i32 %1
280}
281
282define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
283; RV64I-LABEL: zext_addw_zext_aext:
284; RV64I:       # %bb.0:
285; RV64I-NEXT:    add a0, a0, a1
286; RV64I-NEXT:    slli a0, a0, 32
287; RV64I-NEXT:    srli a0, a0, 32
288; RV64I-NEXT:    ret
289;
290; RV64ZBA-LABEL: zext_addw_zext_aext:
291; RV64ZBA:       # %bb.0:
292; RV64ZBA-NEXT:    add a0, a0, a1
293; RV64ZBA-NEXT:    zext.w a0, a0
294; RV64ZBA-NEXT:    ret
295  %1 = add i32 %a, %b
296  ret i32 %1
297}
298
299define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
300; RV64I-LABEL: zext_addw_zext_sext:
301; RV64I:       # %bb.0:
302; RV64I-NEXT:    add a0, a0, a1
303; RV64I-NEXT:    slli a0, a0, 32
304; RV64I-NEXT:    srli a0, a0, 32
305; RV64I-NEXT:    ret
306;
307; RV64ZBA-LABEL: zext_addw_zext_sext:
308; RV64ZBA:       # %bb.0:
309; RV64ZBA-NEXT:    add a0, a0, a1
310; RV64ZBA-NEXT:    zext.w a0, a0
311; RV64ZBA-NEXT:    ret
312  %1 = add i32 %a, %b
313  ret i32 %1
314}
315
316define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
317; RV64I-LABEL: zext_addw_zext_zext:
318; RV64I:       # %bb.0:
319; RV64I-NEXT:    add a0, a0, a1
320; RV64I-NEXT:    slli a0, a0, 32
321; RV64I-NEXT:    srli a0, a0, 32
322; RV64I-NEXT:    ret
323;
324; RV64ZBA-LABEL: zext_addw_zext_zext:
325; RV64ZBA:       # %bb.0:
326; RV64ZBA-NEXT:    add a0, a0, a1
327; RV64ZBA-NEXT:    zext.w a0, a0
328; RV64ZBA-NEXT:    ret
329  %1 = add i32 %a, %b
330  ret i32 %1
331}
332
333; 64-bit sub is safe for an anyext result.
334
335define i32 @aext_subw_aext_aext(i32 %a, i32 %b) nounwind {
336; RV64-LABEL: aext_subw_aext_aext:
337; RV64:       # %bb.0:
338; RV64-NEXT:    subw a0, a0, a1
339; RV64-NEXT:    ret
340  %1 = sub i32 %a, %b
341  ret i32 %1
342}
343
344define i32 @aext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
345; RV64-LABEL: aext_subw_aext_sext:
346; RV64:       # %bb.0:
347; RV64-NEXT:    subw a0, a0, a1
348; RV64-NEXT:    ret
349  %1 = sub i32 %a, %b
350  ret i32 %1
351}
352
353define i32 @aext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
354; RV64-LABEL: aext_subw_aext_zext:
355; RV64:       # %bb.0:
356; RV64-NEXT:    subw a0, a0, a1
357; RV64-NEXT:    ret
358  %1 = sub i32 %a, %b
359  ret i32 %1
360}
361
362define i32 @aext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
363; RV64-LABEL: aext_subw_sext_aext:
364; RV64:       # %bb.0:
365; RV64-NEXT:    subw a0, a0, a1
366; RV64-NEXT:    ret
367  %1 = sub i32 %a, %b
368  ret i32 %1
369}
370
371define i32 @aext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
372; RV64-LABEL: aext_subw_sext_sext:
373; RV64:       # %bb.0:
374; RV64-NEXT:    subw a0, a0, a1
375; RV64-NEXT:    ret
376  %1 = sub i32 %a, %b
377  ret i32 %1
378}
379
380define i32 @aext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
381; RV64-LABEL: aext_subw_sext_zext:
382; RV64:       # %bb.0:
383; RV64-NEXT:    subw a0, a0, a1
384; RV64-NEXT:    ret
385  %1 = sub i32 %a, %b
386  ret i32 %1
387}
388
389define i32 @aext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
390; RV64-LABEL: aext_subw_zext_aext:
391; RV64:       # %bb.0:
392; RV64-NEXT:    subw a0, a0, a1
393; RV64-NEXT:    ret
394  %1 = sub i32 %a, %b
395  ret i32 %1
396}
397
398define i32 @aext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
399; RV64-LABEL: aext_subw_zext_sext:
400; RV64:       # %bb.0:
401; RV64-NEXT:    subw a0, a0, a1
402; RV64-NEXT:    ret
403  %1 = sub i32 %a, %b
404  ret i32 %1
405}
406
407define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
408; RV64-LABEL: aext_subw_zext_zext:
409; RV64:       # %bb.0:
410; RV64-NEXT:    subw a0, a0, a1
411; RV64-NEXT:    ret
412  %1 = sub i32 %a, %b
413  ret i32 %1
414}
415
416; Always select subw for a signext result.
417
418define signext i32 @sext_subw_aext_aext(i32 %a, i32 %b) nounwind {
419; RV64-LABEL: sext_subw_aext_aext:
420; RV64:       # %bb.0:
421; RV64-NEXT:    subw a0, a0, a1
422; RV64-NEXT:    ret
423  %1 = sub i32 %a, %b
424  ret i32 %1
425}
426
427define signext i32 @sext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
428; RV64-LABEL: sext_subw_aext_sext:
429; RV64:       # %bb.0:
430; RV64-NEXT:    subw a0, a0, a1
431; RV64-NEXT:    ret
432  %1 = sub i32 %a, %b
433  ret i32 %1
434}
435
436define signext i32 @sext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
437; RV64-LABEL: sext_subw_aext_zext:
438; RV64:       # %bb.0:
439; RV64-NEXT:    subw a0, a0, a1
440; RV64-NEXT:    ret
441  %1 = sub i32 %a, %b
442  ret i32 %1
443}
444
445define signext i32 @sext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
446; RV64-LABEL: sext_subw_sext_aext:
447; RV64:       # %bb.0:
448; RV64-NEXT:    subw a0, a0, a1
449; RV64-NEXT:    ret
450  %1 = sub i32 %a, %b
451  ret i32 %1
452}
453
454define signext i32 @sext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
455; RV64-LABEL: sext_subw_sext_sext:
456; RV64:       # %bb.0:
457; RV64-NEXT:    subw a0, a0, a1
458; RV64-NEXT:    ret
459  %1 = sub i32 %a, %b
460  ret i32 %1
461}
462
463define signext i32 @sext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
464; RV64-LABEL: sext_subw_sext_zext:
465; RV64:       # %bb.0:
466; RV64-NEXT:    subw a0, a0, a1
467; RV64-NEXT:    ret
468  %1 = sub i32 %a, %b
469  ret i32 %1
470}
471
472define signext i32 @sext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
473; RV64-LABEL: sext_subw_zext_aext:
474; RV64:       # %bb.0:
475; RV64-NEXT:    subw a0, a0, a1
476; RV64-NEXT:    ret
477  %1 = sub i32 %a, %b
478  ret i32 %1
479}
480
481define signext i32 @sext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
482; RV64-LABEL: sext_subw_zext_sext:
483; RV64:       # %bb.0:
484; RV64-NEXT:    subw a0, a0, a1
485; RV64-NEXT:    ret
486  %1 = sub i32 %a, %b
487  ret i32 %1
488}
489
490define signext i32 @sext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
491; RV64-LABEL: sext_subw_zext_zext:
492; RV64:       # %bb.0:
493; RV64-NEXT:    subw a0, a0, a1
494; RV64-NEXT:    ret
495  %1 = sub i32 %a, %b
496  ret i32 %1
497}
498
499; 64-bit sub followed by zero-extension is safe for a zeroext result.
500
501define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {
502; RV64I-LABEL: zext_subw_aext_aext:
503; RV64I:       # %bb.0:
504; RV64I-NEXT:    subw a0, a0, a1
505; RV64I-NEXT:    slli a0, a0, 32
506; RV64I-NEXT:    srli a0, a0, 32
507; RV64I-NEXT:    ret
508;
509; RV64ZBA-LABEL: zext_subw_aext_aext:
510; RV64ZBA:       # %bb.0:
511; RV64ZBA-NEXT:    subw a0, a0, a1
512; RV64ZBA-NEXT:    zext.w a0, a0
513; RV64ZBA-NEXT:    ret
514  %1 = sub i32 %a, %b
515  ret i32 %1
516}
517
518define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
519; RV64I-LABEL: zext_subw_aext_sext:
520; RV64I:       # %bb.0:
521; RV64I-NEXT:    subw a0, a0, a1
522; RV64I-NEXT:    slli a0, a0, 32
523; RV64I-NEXT:    srli a0, a0, 32
524; RV64I-NEXT:    ret
525;
526; RV64ZBA-LABEL: zext_subw_aext_sext:
527; RV64ZBA:       # %bb.0:
528; RV64ZBA-NEXT:    subw a0, a0, a1
529; RV64ZBA-NEXT:    zext.w a0, a0
530; RV64ZBA-NEXT:    ret
531  %1 = sub i32 %a, %b
532  ret i32 %1
533}
534
535define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
536; RV64I-LABEL: zext_subw_aext_zext:
537; RV64I:       # %bb.0:
538; RV64I-NEXT:    subw a0, a0, a1
539; RV64I-NEXT:    slli a0, a0, 32
540; RV64I-NEXT:    srli a0, a0, 32
541; RV64I-NEXT:    ret
542;
543; RV64ZBA-LABEL: zext_subw_aext_zext:
544; RV64ZBA:       # %bb.0:
545; RV64ZBA-NEXT:    subw a0, a0, a1
546; RV64ZBA-NEXT:    zext.w a0, a0
547; RV64ZBA-NEXT:    ret
548  %1 = sub i32 %a, %b
549  ret i32 %1
550}
551
552define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
553; RV64I-LABEL: zext_subw_sext_aext:
554; RV64I:       # %bb.0:
555; RV64I-NEXT:    subw a0, a0, a1
556; RV64I-NEXT:    slli a0, a0, 32
557; RV64I-NEXT:    srli a0, a0, 32
558; RV64I-NEXT:    ret
559;
560; RV64ZBA-LABEL: zext_subw_sext_aext:
561; RV64ZBA:       # %bb.0:
562; RV64ZBA-NEXT:    subw a0, a0, a1
563; RV64ZBA-NEXT:    zext.w a0, a0
564; RV64ZBA-NEXT:    ret
565  %1 = sub i32 %a, %b
566  ret i32 %1
567}
568
569define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
570; RV64I-LABEL: zext_subw_sext_sext:
571; RV64I:       # %bb.0:
572; RV64I-NEXT:    subw a0, a0, a1
573; RV64I-NEXT:    slli a0, a0, 32
574; RV64I-NEXT:    srli a0, a0, 32
575; RV64I-NEXT:    ret
576;
577; RV64ZBA-LABEL: zext_subw_sext_sext:
578; RV64ZBA:       # %bb.0:
579; RV64ZBA-NEXT:    subw a0, a0, a1
580; RV64ZBA-NEXT:    zext.w a0, a0
581; RV64ZBA-NEXT:    ret
582  %1 = sub i32 %a, %b
583  ret i32 %1
584}
585
586define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
587; RV64I-LABEL: zext_subw_sext_zext:
588; RV64I:       # %bb.0:
589; RV64I-NEXT:    subw a0, a0, a1
590; RV64I-NEXT:    slli a0, a0, 32
591; RV64I-NEXT:    srli a0, a0, 32
592; RV64I-NEXT:    ret
593;
594; RV64ZBA-LABEL: zext_subw_sext_zext:
595; RV64ZBA:       # %bb.0:
596; RV64ZBA-NEXT:    subw a0, a0, a1
597; RV64ZBA-NEXT:    zext.w a0, a0
598; RV64ZBA-NEXT:    ret
599  %1 = sub i32 %a, %b
600  ret i32 %1
601}
602
603define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
604; RV64I-LABEL: zext_subw_zext_aext:
605; RV64I:       # %bb.0:
606; RV64I-NEXT:    subw a0, a0, a1
607; RV64I-NEXT:    slli a0, a0, 32
608; RV64I-NEXT:    srli a0, a0, 32
609; RV64I-NEXT:    ret
610;
611; RV64ZBA-LABEL: zext_subw_zext_aext:
612; RV64ZBA:       # %bb.0:
613; RV64ZBA-NEXT:    subw a0, a0, a1
614; RV64ZBA-NEXT:    zext.w a0, a0
615; RV64ZBA-NEXT:    ret
616  %1 = sub i32 %a, %b
617  ret i32 %1
618}
619
620define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
621; RV64I-LABEL: zext_subw_zext_sext:
622; RV64I:       # %bb.0:
623; RV64I-NEXT:    subw a0, a0, a1
624; RV64I-NEXT:    slli a0, a0, 32
625; RV64I-NEXT:    srli a0, a0, 32
626; RV64I-NEXT:    ret
627;
628; RV64ZBA-LABEL: zext_subw_zext_sext:
629; RV64ZBA:       # %bb.0:
630; RV64ZBA-NEXT:    subw a0, a0, a1
631; RV64ZBA-NEXT:    zext.w a0, a0
632; RV64ZBA-NEXT:    ret
633  %1 = sub i32 %a, %b
634  ret i32 %1
635}
636
637define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
638; RV64I-LABEL: zext_subw_zext_zext:
639; RV64I:       # %bb.0:
640; RV64I-NEXT:    subw a0, a0, a1
641; RV64I-NEXT:    slli a0, a0, 32
642; RV64I-NEXT:    srli a0, a0, 32
643; RV64I-NEXT:    ret
644;
645; RV64ZBA-LABEL: zext_subw_zext_zext:
646; RV64ZBA:       # %bb.0:
647; RV64ZBA-NEXT:    subw a0, a0, a1
648; RV64ZBA-NEXT:    zext.w a0, a0
649; RV64ZBA-NEXT:    ret
650  %1 = sub i32 %a, %b
651  ret i32 %1
652}
653
654; 64-bit sll is a safe choice for an anyext result.
655
656define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
657; RV64-LABEL: aext_sllw_aext_aext:
658; RV64:       # %bb.0:
659; RV64-NEXT:    sllw a0, a0, a1
660; RV64-NEXT:    ret
661  %1 = shl i32 %a, %b
662  ret i32 %1
663}
664
665define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
666; RV64-LABEL: aext_sllw_aext_sext:
667; RV64:       # %bb.0:
668; RV64-NEXT:    sllw a0, a0, a1
669; RV64-NEXT:    ret
670  %1 = shl i32 %a, %b
671  ret i32 %1
672}
673
674define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
675; RV64-LABEL: aext_sllw_aext_zext:
676; RV64:       # %bb.0:
677; RV64-NEXT:    sllw a0, a0, a1
678; RV64-NEXT:    ret
679  %1 = shl i32 %a, %b
680  ret i32 %1
681}
682
683define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
684; RV64-LABEL: aext_sllw_sext_aext:
685; RV64:       # %bb.0:
686; RV64-NEXT:    sllw a0, a0, a1
687; RV64-NEXT:    ret
688  %1 = shl i32 %a, %b
689  ret i32 %1
690}
691
692define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
693; RV64-LABEL: aext_sllw_sext_sext:
694; RV64:       # %bb.0:
695; RV64-NEXT:    sllw a0, a0, a1
696; RV64-NEXT:    ret
697  %1 = shl i32 %a, %b
698  ret i32 %1
699}
700
701define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
702; RV64-LABEL: aext_sllw_sext_zext:
703; RV64:       # %bb.0:
704; RV64-NEXT:    sllw a0, a0, a1
705; RV64-NEXT:    ret
706  %1 = shl i32 %a, %b
707  ret i32 %1
708}
709
710define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
711; RV64-LABEL: aext_sllw_zext_aext:
712; RV64:       # %bb.0:
713; RV64-NEXT:    sllw a0, a0, a1
714; RV64-NEXT:    ret
715  %1 = shl i32 %a, %b
716  ret i32 %1
717}
718
719define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
720; RV64-LABEL: aext_sllw_zext_sext:
721; RV64:       # %bb.0:
722; RV64-NEXT:    sllw a0, a0, a1
723; RV64-NEXT:    ret
724  %1 = shl i32 %a, %b
725  ret i32 %1
726}
727
728define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
729; RV64-LABEL: aext_sllw_zext_zext:
730; RV64:       # %bb.0:
731; RV64-NEXT:    sllw a0, a0, a1
732; RV64-NEXT:    ret
733  %1 = shl i32 %a, %b
734  ret i32 %1
735}
736
737define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
738; RV64-LABEL: sext_sllw_aext_aext:
739; RV64:       # %bb.0:
740; RV64-NEXT:    sllw a0, a0, a1
741; RV64-NEXT:    ret
742  %1 = shl i32 %a, %b
743  ret i32 %1
744}
745
746define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
747; RV64-LABEL: sext_sllw_aext_sext:
748; RV64:       # %bb.0:
749; RV64-NEXT:    sllw a0, a0, a1
750; RV64-NEXT:    ret
751  %1 = shl i32 %a, %b
752  ret i32 %1
753}
754
755define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
756; RV64-LABEL: sext_sllw_aext_zext:
757; RV64:       # %bb.0:
758; RV64-NEXT:    sllw a0, a0, a1
759; RV64-NEXT:    ret
760  %1 = shl i32 %a, %b
761  ret i32 %1
762}
763
764define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
765; RV64-LABEL: sext_sllw_sext_aext:
766; RV64:       # %bb.0:
767; RV64-NEXT:    sllw a0, a0, a1
768; RV64-NEXT:    ret
769  %1 = shl i32 %a, %b
770  ret i32 %1
771}
772
773define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
774; RV64-LABEL: sext_sllw_sext_sext:
775; RV64:       # %bb.0:
776; RV64-NEXT:    sllw a0, a0, a1
777; RV64-NEXT:    ret
778  %1 = shl i32 %a, %b
779  ret i32 %1
780}
781
782define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
783; RV64-LABEL: sext_sllw_sext_zext:
784; RV64:       # %bb.0:
785; RV64-NEXT:    sllw a0, a0, a1
786; RV64-NEXT:    ret
787  %1 = shl i32 %a, %b
788  ret i32 %1
789}
790
791define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
792; RV64-LABEL: sext_sllw_zext_aext:
793; RV64:       # %bb.0:
794; RV64-NEXT:    sllw a0, a0, a1
795; RV64-NEXT:    ret
796  %1 = shl i32 %a, %b
797  ret i32 %1
798}
799
800define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
801; RV64-LABEL: sext_sllw_zext_sext:
802; RV64:       # %bb.0:
803; RV64-NEXT:    sllw a0, a0, a1
804; RV64-NEXT:    ret
805  %1 = shl i32 %a, %b
806  ret i32 %1
807}
808
809define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
810; RV64-LABEL: sext_sllw_zext_zext:
811; RV64:       # %bb.0:
812; RV64-NEXT:    sllw a0, a0, a1
813; RV64-NEXT:    ret
814  %1 = shl i32 %a, %b
815  ret i32 %1
816}
817
818; 64-bit sll followed by zero-extension for a zeroext result.
819
820define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
821; RV64I-LABEL: zext_sllw_aext_aext:
822; RV64I:       # %bb.0:
823; RV64I-NEXT:    sllw a0, a0, a1
824; RV64I-NEXT:    slli a0, a0, 32
825; RV64I-NEXT:    srli a0, a0, 32
826; RV64I-NEXT:    ret
827;
828; RV64ZBA-LABEL: zext_sllw_aext_aext:
829; RV64ZBA:       # %bb.0:
830; RV64ZBA-NEXT:    sllw a0, a0, a1
831; RV64ZBA-NEXT:    zext.w a0, a0
832; RV64ZBA-NEXT:    ret
833  %1 = shl i32 %a, %b
834  ret i32 %1
835}
836
837define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
838; RV64I-LABEL: zext_sllw_aext_sext:
839; RV64I:       # %bb.0:
840; RV64I-NEXT:    sllw a0, a0, a1
841; RV64I-NEXT:    slli a0, a0, 32
842; RV64I-NEXT:    srli a0, a0, 32
843; RV64I-NEXT:    ret
844;
845; RV64ZBA-LABEL: zext_sllw_aext_sext:
846; RV64ZBA:       # %bb.0:
847; RV64ZBA-NEXT:    sllw a0, a0, a1
848; RV64ZBA-NEXT:    zext.w a0, a0
849; RV64ZBA-NEXT:    ret
850  %1 = shl i32 %a, %b
851  ret i32 %1
852}
853
854define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
855; RV64I-LABEL: zext_sllw_aext_zext:
856; RV64I:       # %bb.0:
857; RV64I-NEXT:    sllw a0, a0, a1
858; RV64I-NEXT:    slli a0, a0, 32
859; RV64I-NEXT:    srli a0, a0, 32
860; RV64I-NEXT:    ret
861;
862; RV64ZBA-LABEL: zext_sllw_aext_zext:
863; RV64ZBA:       # %bb.0:
864; RV64ZBA-NEXT:    sllw a0, a0, a1
865; RV64ZBA-NEXT:    zext.w a0, a0
866; RV64ZBA-NEXT:    ret
867  %1 = shl i32 %a, %b
868  ret i32 %1
869}
870
871define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
872; RV64I-LABEL: zext_sllw_sext_aext:
873; RV64I:       # %bb.0:
874; RV64I-NEXT:    sllw a0, a0, a1
875; RV64I-NEXT:    slli a0, a0, 32
876; RV64I-NEXT:    srli a0, a0, 32
877; RV64I-NEXT:    ret
878;
879; RV64ZBA-LABEL: zext_sllw_sext_aext:
880; RV64ZBA:       # %bb.0:
881; RV64ZBA-NEXT:    sllw a0, a0, a1
882; RV64ZBA-NEXT:    zext.w a0, a0
883; RV64ZBA-NEXT:    ret
884  %1 = shl i32 %a, %b
885  ret i32 %1
886}
887
888define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
889; RV64I-LABEL: zext_sllw_sext_sext:
890; RV64I:       # %bb.0:
891; RV64I-NEXT:    sllw a0, a0, a1
892; RV64I-NEXT:    slli a0, a0, 32
893; RV64I-NEXT:    srli a0, a0, 32
894; RV64I-NEXT:    ret
895;
896; RV64ZBA-LABEL: zext_sllw_sext_sext:
897; RV64ZBA:       # %bb.0:
898; RV64ZBA-NEXT:    sllw a0, a0, a1
899; RV64ZBA-NEXT:    zext.w a0, a0
900; RV64ZBA-NEXT:    ret
901  %1 = shl i32 %a, %b
902  ret i32 %1
903}
904
905define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
906; RV64I-LABEL: zext_sllw_sext_zext:
907; RV64I:       # %bb.0:
908; RV64I-NEXT:    sllw a0, a0, a1
909; RV64I-NEXT:    slli a0, a0, 32
910; RV64I-NEXT:    srli a0, a0, 32
911; RV64I-NEXT:    ret
912;
913; RV64ZBA-LABEL: zext_sllw_sext_zext:
914; RV64ZBA:       # %bb.0:
915; RV64ZBA-NEXT:    sllw a0, a0, a1
916; RV64ZBA-NEXT:    zext.w a0, a0
917; RV64ZBA-NEXT:    ret
918  %1 = shl i32 %a, %b
919  ret i32 %1
920}
921
922define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
923; RV64I-LABEL: zext_sllw_zext_aext:
924; RV64I:       # %bb.0:
925; RV64I-NEXT:    sllw a0, a0, a1
926; RV64I-NEXT:    slli a0, a0, 32
927; RV64I-NEXT:    srli a0, a0, 32
928; RV64I-NEXT:    ret
929;
930; RV64ZBA-LABEL: zext_sllw_zext_aext:
931; RV64ZBA:       # %bb.0:
932; RV64ZBA-NEXT:    sllw a0, a0, a1
933; RV64ZBA-NEXT:    zext.w a0, a0
934; RV64ZBA-NEXT:    ret
935  %1 = shl i32 %a, %b
936  ret i32 %1
937}
938
939define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
940; RV64I-LABEL: zext_sllw_zext_sext:
941; RV64I:       # %bb.0:
942; RV64I-NEXT:    sllw a0, a0, a1
943; RV64I-NEXT:    slli a0, a0, 32
944; RV64I-NEXT:    srli a0, a0, 32
945; RV64I-NEXT:    ret
946;
947; RV64ZBA-LABEL: zext_sllw_zext_sext:
948; RV64ZBA:       # %bb.0:
949; RV64ZBA-NEXT:    sllw a0, a0, a1
950; RV64ZBA-NEXT:    zext.w a0, a0
951; RV64ZBA-NEXT:    ret
952  %1 = shl i32 %a, %b
953  ret i32 %1
954}
955
956define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
957; RV64I-LABEL: zext_sllw_zext_zext:
958; RV64I:       # %bb.0:
959; RV64I-NEXT:    sllw a0, a0, a1
960; RV64I-NEXT:    slli a0, a0, 32
961; RV64I-NEXT:    srli a0, a0, 32
962; RV64I-NEXT:    ret
963;
964; RV64ZBA-LABEL: zext_sllw_zext_zext:
965; RV64ZBA:       # %bb.0:
966; RV64ZBA-NEXT:    sllw a0, a0, a1
967; RV64ZBA-NEXT:    zext.w a0, a0
968; RV64ZBA-NEXT:    ret
969  %1 = shl i32 %a, %b
970  ret i32 %1
971}
972
973define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
974; RV64-LABEL: aext_srlw_aext_aext:
975; RV64:       # %bb.0:
976; RV64-NEXT:    srlw a0, a0, a1
977; RV64-NEXT:    ret
978  %1 = lshr i32 %a, %b
979  ret i32 %1
980}
981
982define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
983; RV64-LABEL: aext_srlw_aext_sext:
984; RV64:       # %bb.0:
985; RV64-NEXT:    srlw a0, a0, a1
986; RV64-NEXT:    ret
987  %1 = lshr i32 %a, %b
988  ret i32 %1
989}
990
991define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
992; RV64-LABEL: aext_srlw_aext_zext:
993; RV64:       # %bb.0:
994; RV64-NEXT:    srlw a0, a0, a1
995; RV64-NEXT:    ret
996  %1 = lshr i32 %a, %b
997  ret i32 %1
998}
999
1000define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
1001; RV64-LABEL: aext_srlw_sext_aext:
1002; RV64:       # %bb.0:
1003; RV64-NEXT:    srlw a0, a0, a1
1004; RV64-NEXT:    ret
1005  %1 = lshr i32 %a, %b
1006  ret i32 %1
1007}
1008
1009define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1010; RV64-LABEL: aext_srlw_sext_sext:
1011; RV64:       # %bb.0:
1012; RV64-NEXT:    srlw a0, a0, a1
1013; RV64-NEXT:    ret
1014  %1 = lshr i32 %a, %b
1015  ret i32 %1
1016}
1017
1018define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1019; RV64-LABEL: aext_srlw_sext_zext:
1020; RV64:       # %bb.0:
1021; RV64-NEXT:    srlw a0, a0, a1
1022; RV64-NEXT:    ret
1023  %1 = lshr i32 %a, %b
1024  ret i32 %1
1025}
1026
1027define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1028; RV64-LABEL: aext_srlw_zext_aext:
1029; RV64:       # %bb.0:
1030; RV64-NEXT:    srlw a0, a0, a1
1031; RV64-NEXT:    ret
1032  %1 = lshr i32 %a, %b
1033  ret i32 %1
1034}
1035
1036define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1037; RV64-LABEL: aext_srlw_zext_sext:
1038; RV64:       # %bb.0:
1039; RV64-NEXT:    srlw a0, a0, a1
1040; RV64-NEXT:    ret
1041  %1 = lshr i32 %a, %b
1042  ret i32 %1
1043}
1044
1045define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1046; RV64-LABEL: aext_srlw_zext_zext:
1047; RV64:       # %bb.0:
1048; RV64-NEXT:    srlw a0, a0, a1
1049; RV64-NEXT:    ret
1050  %1 = lshr i32 %a, %b
1051  ret i32 %1
1052}
1053
1054define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
1055; RV64-LABEL: sext_srlw_aext_aext:
1056; RV64:       # %bb.0:
1057; RV64-NEXT:    srlw a0, a0, a1
1058; RV64-NEXT:    ret
1059  %1 = lshr i32 %a, %b
1060  ret i32 %1
1061}
1062
1063define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
1064; RV64-LABEL: sext_srlw_aext_sext:
1065; RV64:       # %bb.0:
1066; RV64-NEXT:    srlw a0, a0, a1
1067; RV64-NEXT:    ret
1068  %1 = lshr i32 %a, %b
1069  ret i32 %1
1070}
1071
1072define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1073; RV64-LABEL: sext_srlw_aext_zext:
1074; RV64:       # %bb.0:
1075; RV64-NEXT:    srlw a0, a0, a1
1076; RV64-NEXT:    ret
1077  %1 = lshr i32 %a, %b
1078  ret i32 %1
1079}
1080
1081define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
1082; RV64-LABEL: sext_srlw_sext_aext:
1083; RV64:       # %bb.0:
1084; RV64-NEXT:    srlw a0, a0, a1
1085; RV64-NEXT:    ret
1086  %1 = lshr i32 %a, %b
1087  ret i32 %1
1088}
1089
1090define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1091; RV64-LABEL: sext_srlw_sext_sext:
1092; RV64:       # %bb.0:
1093; RV64-NEXT:    srlw a0, a0, a1
1094; RV64-NEXT:    ret
1095  %1 = lshr i32 %a, %b
1096  ret i32 %1
1097}
1098
1099define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1100; RV64-LABEL: sext_srlw_sext_zext:
1101; RV64:       # %bb.0:
1102; RV64-NEXT:    srlw a0, a0, a1
1103; RV64-NEXT:    ret
1104  %1 = lshr i32 %a, %b
1105  ret i32 %1
1106}
1107
1108define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1109; RV64-LABEL: sext_srlw_zext_aext:
1110; RV64:       # %bb.0:
1111; RV64-NEXT:    srlw a0, a0, a1
1112; RV64-NEXT:    ret
1113  %1 = lshr i32 %a, %b
1114  ret i32 %1
1115}
1116
1117define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1118; RV64-LABEL: sext_srlw_zext_sext:
1119; RV64:       # %bb.0:
1120; RV64-NEXT:    srlw a0, a0, a1
1121; RV64-NEXT:    ret
1122  %1 = lshr i32 %a, %b
1123  ret i32 %1
1124}
1125
1126define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1127; RV64-LABEL: sext_srlw_zext_zext:
1128; RV64:       # %bb.0:
1129; RV64-NEXT:    srlw a0, a0, a1
1130; RV64-NEXT:    ret
1131  %1 = lshr i32 %a, %b
1132  ret i32 %1
1133}
1134
1135define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
1136; RV64I-LABEL: zext_srlw_aext_aext:
1137; RV64I:       # %bb.0:
1138; RV64I-NEXT:    srlw a0, a0, a1
1139; RV64I-NEXT:    slli a0, a0, 32
1140; RV64I-NEXT:    srli a0, a0, 32
1141; RV64I-NEXT:    ret
1142;
1143; RV64ZBA-LABEL: zext_srlw_aext_aext:
1144; RV64ZBA:       # %bb.0:
1145; RV64ZBA-NEXT:    srlw a0, a0, a1
1146; RV64ZBA-NEXT:    zext.w a0, a0
1147; RV64ZBA-NEXT:    ret
1148  %1 = lshr i32 %a, %b
1149  ret i32 %1
1150}
1151
1152define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
1153; RV64I-LABEL: zext_srlw_aext_sext:
1154; RV64I:       # %bb.0:
1155; RV64I-NEXT:    srlw a0, a0, a1
1156; RV64I-NEXT:    slli a0, a0, 32
1157; RV64I-NEXT:    srli a0, a0, 32
1158; RV64I-NEXT:    ret
1159;
1160; RV64ZBA-LABEL: zext_srlw_aext_sext:
1161; RV64ZBA:       # %bb.0:
1162; RV64ZBA-NEXT:    srlw a0, a0, a1
1163; RV64ZBA-NEXT:    zext.w a0, a0
1164; RV64ZBA-NEXT:    ret
1165  %1 = lshr i32 %a, %b
1166  ret i32 %1
1167}
1168
1169define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1170; RV64I-LABEL: zext_srlw_aext_zext:
1171; RV64I:       # %bb.0:
1172; RV64I-NEXT:    srlw a0, a0, a1
1173; RV64I-NEXT:    slli a0, a0, 32
1174; RV64I-NEXT:    srli a0, a0, 32
1175; RV64I-NEXT:    ret
1176;
1177; RV64ZBA-LABEL: zext_srlw_aext_zext:
1178; RV64ZBA:       # %bb.0:
1179; RV64ZBA-NEXT:    srlw a0, a0, a1
1180; RV64ZBA-NEXT:    zext.w a0, a0
1181; RV64ZBA-NEXT:    ret
1182  %1 = lshr i32 %a, %b
1183  ret i32 %1
1184}
1185
1186define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
1187; RV64I-LABEL: zext_srlw_sext_aext:
1188; RV64I:       # %bb.0:
1189; RV64I-NEXT:    srlw a0, a0, a1
1190; RV64I-NEXT:    slli a0, a0, 32
1191; RV64I-NEXT:    srli a0, a0, 32
1192; RV64I-NEXT:    ret
1193;
1194; RV64ZBA-LABEL: zext_srlw_sext_aext:
1195; RV64ZBA:       # %bb.0:
1196; RV64ZBA-NEXT:    srlw a0, a0, a1
1197; RV64ZBA-NEXT:    zext.w a0, a0
1198; RV64ZBA-NEXT:    ret
1199  %1 = lshr i32 %a, %b
1200  ret i32 %1
1201}
1202
1203define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1204; RV64I-LABEL: zext_srlw_sext_sext:
1205; RV64I:       # %bb.0:
1206; RV64I-NEXT:    srlw a0, a0, a1
1207; RV64I-NEXT:    slli a0, a0, 32
1208; RV64I-NEXT:    srli a0, a0, 32
1209; RV64I-NEXT:    ret
1210;
1211; RV64ZBA-LABEL: zext_srlw_sext_sext:
1212; RV64ZBA:       # %bb.0:
1213; RV64ZBA-NEXT:    srlw a0, a0, a1
1214; RV64ZBA-NEXT:    zext.w a0, a0
1215; RV64ZBA-NEXT:    ret
1216  %1 = lshr i32 %a, %b
1217  ret i32 %1
1218}
1219
1220define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1221; RV64I-LABEL: zext_srlw_sext_zext:
1222; RV64I:       # %bb.0:
1223; RV64I-NEXT:    srlw a0, a0, a1
1224; RV64I-NEXT:    slli a0, a0, 32
1225; RV64I-NEXT:    srli a0, a0, 32
1226; RV64I-NEXT:    ret
1227;
1228; RV64ZBA-LABEL: zext_srlw_sext_zext:
1229; RV64ZBA:       # %bb.0:
1230; RV64ZBA-NEXT:    srlw a0, a0, a1
1231; RV64ZBA-NEXT:    zext.w a0, a0
1232; RV64ZBA-NEXT:    ret
1233  %1 = lshr i32 %a, %b
1234  ret i32 %1
1235}
1236
1237define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1238; RV64I-LABEL: zext_srlw_zext_aext:
1239; RV64I:       # %bb.0:
1240; RV64I-NEXT:    srlw a0, a0, a1
1241; RV64I-NEXT:    slli a0, a0, 32
1242; RV64I-NEXT:    srli a0, a0, 32
1243; RV64I-NEXT:    ret
1244;
1245; RV64ZBA-LABEL: zext_srlw_zext_aext:
1246; RV64ZBA:       # %bb.0:
1247; RV64ZBA-NEXT:    srlw a0, a0, a1
1248; RV64ZBA-NEXT:    zext.w a0, a0
1249; RV64ZBA-NEXT:    ret
1250  %1 = lshr i32 %a, %b
1251  ret i32 %1
1252}
1253
1254define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1255; RV64I-LABEL: zext_srlw_zext_sext:
1256; RV64I:       # %bb.0:
1257; RV64I-NEXT:    srlw a0, a0, a1
1258; RV64I-NEXT:    slli a0, a0, 32
1259; RV64I-NEXT:    srli a0, a0, 32
1260; RV64I-NEXT:    ret
1261;
1262; RV64ZBA-LABEL: zext_srlw_zext_sext:
1263; RV64ZBA:       # %bb.0:
1264; RV64ZBA-NEXT:    srlw a0, a0, a1
1265; RV64ZBA-NEXT:    zext.w a0, a0
1266; RV64ZBA-NEXT:    ret
1267  %1 = lshr i32 %a, %b
1268  ret i32 %1
1269}
1270
1271define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1272; RV64I-LABEL: zext_srlw_zext_zext:
1273; RV64I:       # %bb.0:
1274; RV64I-NEXT:    srlw a0, a0, a1
1275; RV64I-NEXT:    slli a0, a0, 32
1276; RV64I-NEXT:    srli a0, a0, 32
1277; RV64I-NEXT:    ret
1278;
1279; RV64ZBA-LABEL: zext_srlw_zext_zext:
1280; RV64ZBA:       # %bb.0:
1281; RV64ZBA-NEXT:    srlw a0, a0, a1
1282; RV64ZBA-NEXT:    zext.w a0, a0
1283; RV64ZBA-NEXT:    ret
1284  %1 = lshr i32 %a, %b
1285  ret i32 %1
1286}
1287
1288define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1289; RV64-LABEL: aext_sraw_aext_aext:
1290; RV64:       # %bb.0:
1291; RV64-NEXT:    sraw a0, a0, a1
1292; RV64-NEXT:    ret
1293  %1 = ashr i32 %a, %b
1294  ret i32 %1
1295}
1296
1297define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1298; RV64-LABEL: aext_sraw_aext_sext:
1299; RV64:       # %bb.0:
1300; RV64-NEXT:    sraw a0, a0, a1
1301; RV64-NEXT:    ret
1302  %1 = ashr i32 %a, %b
1303  ret i32 %1
1304}
1305
1306define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1307; RV64-LABEL: aext_sraw_aext_zext:
1308; RV64:       # %bb.0:
1309; RV64-NEXT:    sraw a0, a0, a1
1310; RV64-NEXT:    ret
1311  %1 = ashr i32 %a, %b
1312  ret i32 %1
1313}
1314
1315define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1316; RV64-LABEL: aext_sraw_sext_aext:
1317; RV64:       # %bb.0:
1318; RV64-NEXT:    sraw a0, a0, a1
1319; RV64-NEXT:    ret
1320  %1 = ashr i32 %a, %b
1321  ret i32 %1
1322}
1323
1324define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1325; RV64-LABEL: aext_sraw_sext_sext:
1326; RV64:       # %bb.0:
1327; RV64-NEXT:    sraw a0, a0, a1
1328; RV64-NEXT:    ret
1329  %1 = ashr i32 %a, %b
1330  ret i32 %1
1331}
1332
1333define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1334; RV64-LABEL: aext_sraw_sext_zext:
1335; RV64:       # %bb.0:
1336; RV64-NEXT:    sraw a0, a0, a1
1337; RV64-NEXT:    ret
1338  %1 = ashr i32 %a, %b
1339  ret i32 %1
1340}
1341
1342define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1343; RV64-LABEL: aext_sraw_zext_aext:
1344; RV64:       # %bb.0:
1345; RV64-NEXT:    sraw a0, a0, a1
1346; RV64-NEXT:    ret
1347  %1 = ashr i32 %a, %b
1348  ret i32 %1
1349}
1350
1351define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1352; RV64-LABEL: aext_sraw_zext_sext:
1353; RV64:       # %bb.0:
1354; RV64-NEXT:    sraw a0, a0, a1
1355; RV64-NEXT:    ret
1356  %1 = ashr i32 %a, %b
1357  ret i32 %1
1358}
1359
1360define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1361; RV64-LABEL: aext_sraw_zext_zext:
1362; RV64:       # %bb.0:
1363; RV64-NEXT:    sraw a0, a0, a1
1364; RV64-NEXT:    ret
1365  %1 = ashr i32 %a, %b
1366  ret i32 %1
1367}
1368
1369define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1370; RV64-LABEL: sext_sraw_aext_aext:
1371; RV64:       # %bb.0:
1372; RV64-NEXT:    sraw a0, a0, a1
1373; RV64-NEXT:    ret
1374  %1 = ashr i32 %a, %b
1375  ret i32 %1
1376}
1377
1378define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1379; RV64-LABEL: sext_sraw_aext_sext:
1380; RV64:       # %bb.0:
1381; RV64-NEXT:    sraw a0, a0, a1
1382; RV64-NEXT:    ret
1383  %1 = ashr i32 %a, %b
1384  ret i32 %1
1385}
1386
1387define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1388; RV64-LABEL: sext_sraw_aext_zext:
1389; RV64:       # %bb.0:
1390; RV64-NEXT:    sraw a0, a0, a1
1391; RV64-NEXT:    ret
1392  %1 = ashr i32 %a, %b
1393  ret i32 %1
1394}
1395
1396define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1397; RV64-LABEL: sext_sraw_sext_aext:
1398; RV64:       # %bb.0:
1399; RV64-NEXT:    sraw a0, a0, a1
1400; RV64-NEXT:    ret
1401  %1 = ashr i32 %a, %b
1402  ret i32 %1
1403}
1404
1405define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1406; RV64-LABEL: sext_sraw_sext_sext:
1407; RV64:       # %bb.0:
1408; RV64-NEXT:    sraw a0, a0, a1
1409; RV64-NEXT:    ret
1410  %1 = ashr i32 %a, %b
1411  ret i32 %1
1412}
1413
1414define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1415; RV64-LABEL: sext_sraw_sext_zext:
1416; RV64:       # %bb.0:
1417; RV64-NEXT:    sraw a0, a0, a1
1418; RV64-NEXT:    ret
1419  %1 = ashr i32 %a, %b
1420  ret i32 %1
1421}
1422
1423define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1424; RV64-LABEL: sext_sraw_zext_aext:
1425; RV64:       # %bb.0:
1426; RV64-NEXT:    sraw a0, a0, a1
1427; RV64-NEXT:    ret
1428  %1 = ashr i32 %a, %b
1429  ret i32 %1
1430}
1431
1432define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1433; RV64-LABEL: sext_sraw_zext_sext:
1434; RV64:       # %bb.0:
1435; RV64-NEXT:    sraw a0, a0, a1
1436; RV64-NEXT:    ret
1437  %1 = ashr i32 %a, %b
1438  ret i32 %1
1439}
1440
1441define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1442; RV64-LABEL: sext_sraw_zext_zext:
1443; RV64:       # %bb.0:
1444; RV64-NEXT:    sraw a0, a0, a1
1445; RV64-NEXT:    ret
1446  %1 = ashr i32 %a, %b
1447  ret i32 %1
1448}
1449
1450define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1451; RV64I-LABEL: zext_sraw_aext_aext:
1452; RV64I:       # %bb.0:
1453; RV64I-NEXT:    sraw a0, a0, a1
1454; RV64I-NEXT:    slli a0, a0, 32
1455; RV64I-NEXT:    srli a0, a0, 32
1456; RV64I-NEXT:    ret
1457;
1458; RV64ZBA-LABEL: zext_sraw_aext_aext:
1459; RV64ZBA:       # %bb.0:
1460; RV64ZBA-NEXT:    sraw a0, a0, a1
1461; RV64ZBA-NEXT:    zext.w a0, a0
1462; RV64ZBA-NEXT:    ret
1463  %1 = ashr i32 %a, %b
1464  ret i32 %1
1465}
1466
1467define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1468; RV64I-LABEL: zext_sraw_aext_sext:
1469; RV64I:       # %bb.0:
1470; RV64I-NEXT:    sraw a0, a0, a1
1471; RV64I-NEXT:    slli a0, a0, 32
1472; RV64I-NEXT:    srli a0, a0, 32
1473; RV64I-NEXT:    ret
1474;
1475; RV64ZBA-LABEL: zext_sraw_aext_sext:
1476; RV64ZBA:       # %bb.0:
1477; RV64ZBA-NEXT:    sraw a0, a0, a1
1478; RV64ZBA-NEXT:    zext.w a0, a0
1479; RV64ZBA-NEXT:    ret
1480  %1 = ashr i32 %a, %b
1481  ret i32 %1
1482}
1483
1484define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1485; RV64I-LABEL: zext_sraw_aext_zext:
1486; RV64I:       # %bb.0:
1487; RV64I-NEXT:    sraw a0, a0, a1
1488; RV64I-NEXT:    slli a0, a0, 32
1489; RV64I-NEXT:    srli a0, a0, 32
1490; RV64I-NEXT:    ret
1491;
1492; RV64ZBA-LABEL: zext_sraw_aext_zext:
1493; RV64ZBA:       # %bb.0:
1494; RV64ZBA-NEXT:    sraw a0, a0, a1
1495; RV64ZBA-NEXT:    zext.w a0, a0
1496; RV64ZBA-NEXT:    ret
1497  %1 = ashr i32 %a, %b
1498  ret i32 %1
1499}
1500
1501define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1502; RV64I-LABEL: zext_sraw_sext_aext:
1503; RV64I:       # %bb.0:
1504; RV64I-NEXT:    sraw a0, a0, a1
1505; RV64I-NEXT:    slli a0, a0, 32
1506; RV64I-NEXT:    srli a0, a0, 32
1507; RV64I-NEXT:    ret
1508;
1509; RV64ZBA-LABEL: zext_sraw_sext_aext:
1510; RV64ZBA:       # %bb.0:
1511; RV64ZBA-NEXT:    sraw a0, a0, a1
1512; RV64ZBA-NEXT:    zext.w a0, a0
1513; RV64ZBA-NEXT:    ret
1514  %1 = ashr i32 %a, %b
1515  ret i32 %1
1516}
1517
1518define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1519; RV64I-LABEL: zext_sraw_sext_sext:
1520; RV64I:       # %bb.0:
1521; RV64I-NEXT:    sraw a0, a0, a1
1522; RV64I-NEXT:    slli a0, a0, 32
1523; RV64I-NEXT:    srli a0, a0, 32
1524; RV64I-NEXT:    ret
1525;
1526; RV64ZBA-LABEL: zext_sraw_sext_sext:
1527; RV64ZBA:       # %bb.0:
1528; RV64ZBA-NEXT:    sraw a0, a0, a1
1529; RV64ZBA-NEXT:    zext.w a0, a0
1530; RV64ZBA-NEXT:    ret
1531  %1 = ashr i32 %a, %b
1532  ret i32 %1
1533}
1534
1535define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1536; RV64I-LABEL: zext_sraw_sext_zext:
1537; RV64I:       # %bb.0:
1538; RV64I-NEXT:    sraw a0, a0, a1
1539; RV64I-NEXT:    slli a0, a0, 32
1540; RV64I-NEXT:    srli a0, a0, 32
1541; RV64I-NEXT:    ret
1542;
1543; RV64ZBA-LABEL: zext_sraw_sext_zext:
1544; RV64ZBA:       # %bb.0:
1545; RV64ZBA-NEXT:    sraw a0, a0, a1
1546; RV64ZBA-NEXT:    zext.w a0, a0
1547; RV64ZBA-NEXT:    ret
1548  %1 = ashr i32 %a, %b
1549  ret i32 %1
1550}
1551
1552define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1553; RV64I-LABEL: zext_sraw_zext_aext:
1554; RV64I:       # %bb.0:
1555; RV64I-NEXT:    sraw a0, a0, a1
1556; RV64I-NEXT:    slli a0, a0, 32
1557; RV64I-NEXT:    srli a0, a0, 32
1558; RV64I-NEXT:    ret
1559;
1560; RV64ZBA-LABEL: zext_sraw_zext_aext:
1561; RV64ZBA:       # %bb.0:
1562; RV64ZBA-NEXT:    sraw a0, a0, a1
1563; RV64ZBA-NEXT:    zext.w a0, a0
1564; RV64ZBA-NEXT:    ret
1565  %1 = ashr i32 %a, %b
1566  ret i32 %1
1567}
1568
1569define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1570; RV64I-LABEL: zext_sraw_zext_sext:
1571; RV64I:       # %bb.0:
1572; RV64I-NEXT:    sraw a0, a0, a1
1573; RV64I-NEXT:    slli a0, a0, 32
1574; RV64I-NEXT:    srli a0, a0, 32
1575; RV64I-NEXT:    ret
1576;
1577; RV64ZBA-LABEL: zext_sraw_zext_sext:
1578; RV64ZBA:       # %bb.0:
1579; RV64ZBA-NEXT:    sraw a0, a0, a1
1580; RV64ZBA-NEXT:    zext.w a0, a0
1581; RV64ZBA-NEXT:    ret
1582  %1 = ashr i32 %a, %b
1583  ret i32 %1
1584}
1585
1586define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1587; RV64I-LABEL: zext_sraw_zext_zext:
1588; RV64I:       # %bb.0:
1589; RV64I-NEXT:    sraw a0, a0, a1
1590; RV64I-NEXT:    slli a0, a0, 32
1591; RV64I-NEXT:    srli a0, a0, 32
1592; RV64I-NEXT:    ret
1593;
1594; RV64ZBA-LABEL: zext_sraw_zext_zext:
1595; RV64ZBA:       # %bb.0:
1596; RV64ZBA-NEXT:    sraw a0, a0, a1
1597; RV64ZBA-NEXT:    zext.w a0, a0
1598; RV64ZBA-NEXT:    ret
1599  %1 = ashr i32 %a, %b
1600  ret i32 %1
1601}
1602
1603; addiw should be selected when there is a signext result.
1604
1605define i32 @aext_addiw_aext(i32 %a) nounwind {
1606; RV64-LABEL: aext_addiw_aext:
1607; RV64:       # %bb.0:
1608; RV64-NEXT:    addiw a0, a0, 1
1609; RV64-NEXT:    ret
1610  %1 = add i32 %a, 1
1611  ret i32 %1
1612}
1613
1614define i32 @aext_addiw_sext(i32 signext %a) nounwind {
1615; RV64-LABEL: aext_addiw_sext:
1616; RV64:       # %bb.0:
1617; RV64-NEXT:    addiw a0, a0, 2
1618; RV64-NEXT:    ret
1619  %1 = add i32 %a, 2
1620  ret i32 %1
1621}
1622
1623define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
1624; RV64-LABEL: aext_addiw_zext:
1625; RV64:       # %bb.0:
1626; RV64-NEXT:    addiw a0, a0, 3
1627; RV64-NEXT:    ret
1628  %1 = add i32 %a, 3
1629  ret i32 %1
1630}
1631
1632define signext i32 @sext_addiw_aext(i32 %a) nounwind {
1633; RV64-LABEL: sext_addiw_aext:
1634; RV64:       # %bb.0:
1635; RV64-NEXT:    addiw a0, a0, 4
1636; RV64-NEXT:    ret
1637  %1 = add i32 %a, 4
1638  ret i32 %1
1639}
1640
1641define signext i32 @sext_addiw_sext(i32 signext %a) nounwind {
1642; RV64-LABEL: sext_addiw_sext:
1643; RV64:       # %bb.0:
1644; RV64-NEXT:    addiw a0, a0, 5
1645; RV64-NEXT:    ret
1646  %1 = add i32 %a, 5
1647  ret i32 %1
1648}
1649
1650define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {
1651; RV64-LABEL: sext_addiw_zext:
1652; RV64:       # %bb.0:
1653; RV64-NEXT:    addiw a0, a0, 6
1654; RV64-NEXT:    ret
1655  %1 = add i32 %a, 6
1656  ret i32 %1
1657}
1658
1659define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
1660; RV64I-LABEL: zext_addiw_aext:
1661; RV64I:       # %bb.0:
1662; RV64I-NEXT:    addi a0, a0, 7
1663; RV64I-NEXT:    slli a0, a0, 32
1664; RV64I-NEXT:    srli a0, a0, 32
1665; RV64I-NEXT:    ret
1666;
1667; RV64ZBA-LABEL: zext_addiw_aext:
1668; RV64ZBA:       # %bb.0:
1669; RV64ZBA-NEXT:    addi a0, a0, 7
1670; RV64ZBA-NEXT:    zext.w a0, a0
1671; RV64ZBA-NEXT:    ret
1672  %1 = add i32 %a, 7
1673  ret i32 %1
1674}
1675
1676define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
1677; RV64I-LABEL: zext_addiw_sext:
1678; RV64I:       # %bb.0:
1679; RV64I-NEXT:    addi a0, a0, 8
1680; RV64I-NEXT:    slli a0, a0, 32
1681; RV64I-NEXT:    srli a0, a0, 32
1682; RV64I-NEXT:    ret
1683;
1684; RV64ZBA-LABEL: zext_addiw_sext:
1685; RV64ZBA:       # %bb.0:
1686; RV64ZBA-NEXT:    addi a0, a0, 8
1687; RV64ZBA-NEXT:    zext.w a0, a0
1688; RV64ZBA-NEXT:    ret
1689  %1 = add i32 %a, 8
1690  ret i32 %1
1691}
1692
1693define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
1694; RV64I-LABEL: zext_addiw_zext:
1695; RV64I:       # %bb.0:
1696; RV64I-NEXT:    addi a0, a0, 9
1697; RV64I-NEXT:    slli a0, a0, 32
1698; RV64I-NEXT:    srli a0, a0, 32
1699; RV64I-NEXT:    ret
1700;
1701; RV64ZBA-LABEL: zext_addiw_zext:
1702; RV64ZBA:       # %bb.0:
1703; RV64ZBA-NEXT:    addi a0, a0, 9
1704; RV64ZBA-NEXT:    zext.w a0, a0
1705; RV64ZBA-NEXT:    ret
1706  %1 = add i32 %a, 9
1707  ret i32 %1
1708}
1709
1710; slliw should be selected whenever the return is signext.
1711
1712define i32 @aext_slliw_aext(i32 %a) nounwind {
1713; RV64-LABEL: aext_slliw_aext:
1714; RV64:       # %bb.0:
1715; RV64-NEXT:    slliw a0, a0, 1
1716; RV64-NEXT:    ret
1717  %1 = shl i32 %a, 1
1718  ret i32 %1
1719}
1720
1721define i32 @aext_slliw_sext(i32 signext %a) nounwind {
1722; RV64-LABEL: aext_slliw_sext:
1723; RV64:       # %bb.0:
1724; RV64-NEXT:    slliw a0, a0, 2
1725; RV64-NEXT:    ret
1726  %1 = shl i32 %a, 2
1727  ret i32 %1
1728}
1729
1730define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
1731; RV64-LABEL: aext_slliw_zext:
1732; RV64:       # %bb.0:
1733; RV64-NEXT:    slliw a0, a0, 3
1734; RV64-NEXT:    ret
1735  %1 = shl i32 %a, 3
1736  ret i32 %1
1737}
1738
1739define signext i32 @sext_slliw_aext(i32 %a) nounwind {
1740; RV64-LABEL: sext_slliw_aext:
1741; RV64:       # %bb.0:
1742; RV64-NEXT:    slliw a0, a0, 4
1743; RV64-NEXT:    ret
1744  %1 = shl i32 %a, 4
1745  ret i32 %1
1746}
1747
1748define signext i32 @sext_slliw_sext(i32 signext %a) nounwind {
1749; RV64-LABEL: sext_slliw_sext:
1750; RV64:       # %bb.0:
1751; RV64-NEXT:    slliw a0, a0, 5
1752; RV64-NEXT:    ret
1753  %1 = shl i32 %a, 5
1754  ret i32 %1
1755}
1756
1757define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {
1758; RV64-LABEL: sext_slliw_zext:
1759; RV64:       # %bb.0:
1760; RV64-NEXT:    slliw a0, a0, 6
1761; RV64-NEXT:    ret
1762  %1 = shl i32 %a, 6
1763  ret i32 %1
1764}
1765
1766define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {
1767; RV64-LABEL: zext_slliw_aext:
1768; RV64:       # %bb.0:
1769; RV64-NEXT:    slli a0, a0, 39
1770; RV64-NEXT:    srli a0, a0, 32
1771; RV64-NEXT:    ret
1772  %1 = shl i32 %a, 7
1773  ret i32 %1
1774}
1775
1776define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {
1777; RV64-LABEL: zext_slliw_sext:
1778; RV64:       # %bb.0:
1779; RV64-NEXT:    slli a0, a0, 40
1780; RV64-NEXT:    srli a0, a0, 32
1781; RV64-NEXT:    ret
1782  %1 = shl i32 %a, 8
1783  ret i32 %1
1784}
1785
1786define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
1787; RV64-LABEL: zext_slliw_zext:
1788; RV64:       # %bb.0:
1789; RV64-NEXT:    slli a0, a0, 41
1790; RV64-NEXT:    srli a0, a0, 32
1791; RV64-NEXT:    ret
1792  %1 = shl i32 %a, 9
1793  ret i32 %1
1794}
1795
1796; srliw should be selected unless the first operand is zeroext, when srli is
1797; equivalent.
1798
1799define i32 @aext_srliw_aext(i32 %a) nounwind {
1800; RV64-LABEL: aext_srliw_aext:
1801; RV64:       # %bb.0:
1802; RV64-NEXT:    srliw a0, a0, 1
1803; RV64-NEXT:    ret
1804  %1 = lshr i32 %a, 1
1805  ret i32 %1
1806}
1807
1808define i32 @aext_srliw_sext(i32 signext %a) nounwind {
1809; RV64-LABEL: aext_srliw_sext:
1810; RV64:       # %bb.0:
1811; RV64-NEXT:    srliw a0, a0, 2
1812; RV64-NEXT:    ret
1813  %1 = lshr i32 %a, 2
1814  ret i32 %1
1815}
1816
1817define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
1818; RV64-LABEL: aext_srliw_zext:
1819; RV64:       # %bb.0:
1820; RV64-NEXT:    srli a0, a0, 3
1821; RV64-NEXT:    ret
1822  %1 = lshr i32 %a, 3
1823  ret i32 %1
1824}
1825
1826define signext i32 @sext_srliw_aext(i32 %a) nounwind {
1827; RV64-LABEL: sext_srliw_aext:
1828; RV64:       # %bb.0:
1829; RV64-NEXT:    srliw a0, a0, 4
1830; RV64-NEXT:    ret
1831  %1 = lshr i32 %a, 4
1832  ret i32 %1
1833}
1834
1835define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
1836; RV64-LABEL: sext_srliw_sext:
1837; RV64:       # %bb.0:
1838; RV64-NEXT:    srliw a0, a0, 5
1839; RV64-NEXT:    ret
1840  %1 = lshr i32 %a, 5
1841  ret i32 %1
1842}
1843
1844define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
1845; RV64-LABEL: sext_srliw_zext:
1846; RV64:       # %bb.0:
1847; RV64-NEXT:    srli a0, a0, 6
1848; RV64-NEXT:    ret
1849  %1 = lshr i32 %a, 6
1850  ret i32 %1
1851}
1852
1853define zeroext i32 @zext_srliw_aext(i32 %a) nounwind {
1854; RV64-LABEL: zext_srliw_aext:
1855; RV64:       # %bb.0:
1856; RV64-NEXT:    srliw a0, a0, 7
1857; RV64-NEXT:    ret
1858  %1 = lshr i32 %a, 7
1859  ret i32 %1
1860}
1861
1862define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
1863; RV64-LABEL: zext_srliw_sext:
1864; RV64:       # %bb.0:
1865; RV64-NEXT:    srliw a0, a0, 8
1866; RV64-NEXT:    ret
1867  %1 = lshr i32 %a, 8
1868  ret i32 %1
1869}
1870
1871define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
1872; RV64-LABEL: zext_srliw_zext:
1873; RV64:       # %bb.0:
1874; RV64-NEXT:    srli a0, a0, 9
1875; RV64-NEXT:    ret
1876  %1 = lshr i32 %a, 9
1877  ret i32 %1
1878}
1879
1880; srai is equivalent to sraiw if the first operand is sign-extended.
1881
1882define i32 @aext_sraiw_aext(i32 %a) nounwind {
1883; RV64-LABEL: aext_sraiw_aext:
1884; RV64:       # %bb.0:
1885; RV64-NEXT:    sraiw a0, a0, 1
1886; RV64-NEXT:    ret
1887  %1 = ashr i32 %a, 1
1888  ret i32 %1
1889}
1890
1891define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
1892; RV64-LABEL: aext_sraiw_sext:
1893; RV64:       # %bb.0:
1894; RV64-NEXT:    srai a0, a0, 2
1895; RV64-NEXT:    ret
1896  %1 = ashr i32 %a, 2
1897  ret i32 %1
1898}
1899
1900define i32 @aext_sraiw_zext(i32 zeroext %a) nounwind {
1901; RV64-LABEL: aext_sraiw_zext:
1902; RV64:       # %bb.0:
1903; RV64-NEXT:    sraiw a0, a0, 3
1904; RV64-NEXT:    ret
1905  %1 = ashr i32 %a, 3
1906  ret i32 %1
1907}
1908
1909define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
1910; RV64-LABEL: sext_sraiw_aext:
1911; RV64:       # %bb.0:
1912; RV64-NEXT:    sraiw a0, a0, 4
1913; RV64-NEXT:    ret
1914  %1 = ashr i32 %a, 4
1915  ret i32 %1
1916}
1917
1918define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
1919; RV64-LABEL: sext_sraiw_sext:
1920; RV64:       # %bb.0:
1921; RV64-NEXT:    srai a0, a0, 5
1922; RV64-NEXT:    ret
1923  %1 = ashr i32 %a, 5
1924  ret i32 %1
1925}
1926
1927define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
1928; RV64-LABEL: sext_sraiw_zext:
1929; RV64:       # %bb.0:
1930; RV64-NEXT:    sraiw a0, a0, 6
1931; RV64-NEXT:    ret
1932  %1 = ashr i32 %a, 6
1933  ret i32 %1
1934}
1935
1936define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
1937; RV64I-LABEL: zext_sraiw_aext:
1938; RV64I:       # %bb.0:
1939; RV64I-NEXT:    sext.w a0, a0
1940; RV64I-NEXT:    slli a0, a0, 25
1941; RV64I-NEXT:    srli a0, a0, 32
1942; RV64I-NEXT:    ret
1943;
1944; RV64ZBA-LABEL: zext_sraiw_aext:
1945; RV64ZBA:       # %bb.0:
1946; RV64ZBA-NEXT:    sraiw a0, a0, 7
1947; RV64ZBA-NEXT:    zext.w a0, a0
1948; RV64ZBA-NEXT:    ret
1949  %1 = ashr i32 %a, 7
1950  ret i32 %1
1951}
1952
1953define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
1954; RV64-LABEL: zext_sraiw_sext:
1955; RV64:       # %bb.0:
1956; RV64-NEXT:    slli a0, a0, 24
1957; RV64-NEXT:    srli a0, a0, 32
1958; RV64-NEXT:    ret
1959  %1 = ashr i32 %a, 8
1960  ret i32 %1
1961}
1962
1963define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
1964; RV64I-LABEL: zext_sraiw_zext:
1965; RV64I:       # %bb.0:
1966; RV64I-NEXT:    sext.w a0, a0
1967; RV64I-NEXT:    slli a0, a0, 23
1968; RV64I-NEXT:    srli a0, a0, 32
1969; RV64I-NEXT:    ret
1970;
1971; RV64ZBA-LABEL: zext_sraiw_zext:
1972; RV64ZBA:       # %bb.0:
1973; RV64ZBA-NEXT:    sraiw a0, a0, 9
1974; RV64ZBA-NEXT:    zext.w a0, a0
1975; RV64ZBA-NEXT:    ret
1976  %1 = ashr i32 %a, 9
1977  ret i32 %1
1978}
1979