1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV64IF 4; RUN: llc -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64IZFINX 6 7; This file exhaustively checks float<->i32 conversions. In general, 8; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is 9; generated for an fpto[s|u]i conversion if the result doesn't fit in the 10; target type. 11 12define i32 @aext_fptosi(float %a) nounwind { 13; RV64IF-LABEL: aext_fptosi: 14; RV64IF: # %bb.0: 15; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz 16; RV64IF-NEXT: ret 17; 18; RV64IZFINX-LABEL: aext_fptosi: 19; RV64IZFINX: # %bb.0: 20; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rtz 21; RV64IZFINX-NEXT: ret 22 %1 = fptosi float %a to i32 23 ret i32 %1 24} 25 26define signext i32 @sext_fptosi(float %a) nounwind { 27; RV64IF-LABEL: sext_fptosi: 28; RV64IF: # %bb.0: 29; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz 30; RV64IF-NEXT: ret 31; 32; RV64IZFINX-LABEL: sext_fptosi: 33; RV64IZFINX: # %bb.0: 34; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rtz 35; RV64IZFINX-NEXT: ret 36 %1 = fptosi float %a to i32 37 ret i32 %1 38} 39 40define zeroext i32 @zext_fptosi(float %a) nounwind { 41; RV64IF-LABEL: zext_fptosi: 42; RV64IF: # %bb.0: 43; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz 44; RV64IF-NEXT: slli a0, a0, 32 45; RV64IF-NEXT: srli a0, a0, 32 46; RV64IF-NEXT: ret 47; 48; RV64IZFINX-LABEL: zext_fptosi: 49; RV64IZFINX: # %bb.0: 50; RV64IZFINX-NEXT: fcvt.w.s a0, a0, rtz 51; RV64IZFINX-NEXT: slli a0, a0, 32 52; RV64IZFINX-NEXT: srli a0, a0, 32 53; RV64IZFINX-NEXT: ret 54 %1 = fptosi float %a to i32 55 ret i32 %1 56} 57 58define i32 @aext_fptoui(float %a) nounwind { 59; RV64IF-LABEL: aext_fptoui: 60; RV64IF: # %bb.0: 61; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz 62; RV64IF-NEXT: ret 63; 64; RV64IZFINX-LABEL: aext_fptoui: 65; RV64IZFINX: # %bb.0: 66; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 67; RV64IZFINX-NEXT: ret 68 %1 = fptoui float %a to i32 69 ret i32 %1 70} 71 72define signext i32 @sext_fptoui(float %a) nounwind { 73; RV64IF-LABEL: sext_fptoui: 74; RV64IF: # %bb.0: 75; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz 76; RV64IF-NEXT: ret 77; 78; RV64IZFINX-LABEL: sext_fptoui: 79; RV64IZFINX: # %bb.0: 80; RV64IZFINX-NEXT: fcvt.wu.s a0, a0, rtz 81; RV64IZFINX-NEXT: ret 82 %1 = fptoui float %a to i32 83 ret i32 %1 84} 85 86define zeroext i32 @zext_fptoui(float %a) nounwind { 87; RV64IF-LABEL: zext_fptoui: 88; RV64IF: # %bb.0: 89; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz 90; RV64IF-NEXT: ret 91; 92; RV64IZFINX-LABEL: zext_fptoui: 93; RV64IZFINX: # %bb.0: 94; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz 95; RV64IZFINX-NEXT: ret 96 %1 = fptoui float %a to i32 97 ret i32 %1 98} 99 100define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind { 101; RV64IF-LABEL: bcvt_f32_to_aext_i32: 102; RV64IF: # %bb.0: 103; RV64IF-NEXT: fadd.s fa5, fa0, fa1 104; RV64IF-NEXT: fmv.x.w a0, fa5 105; RV64IF-NEXT: ret 106; 107; RV64IZFINX-LABEL: bcvt_f32_to_aext_i32: 108; RV64IZFINX: # %bb.0: 109; RV64IZFINX-NEXT: fadd.s a0, a0, a1 110; RV64IZFINX-NEXT: ret 111 %1 = fadd float %a, %b 112 %2 = bitcast float %1 to i32 113 ret i32 %2 114} 115 116define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind { 117; RV64IF-LABEL: bcvt_f32_to_sext_i32: 118; RV64IF: # %bb.0: 119; RV64IF-NEXT: fadd.s fa5, fa0, fa1 120; RV64IF-NEXT: fmv.x.w a0, fa5 121; RV64IF-NEXT: ret 122; 123; RV64IZFINX-LABEL: bcvt_f32_to_sext_i32: 124; RV64IZFINX: # %bb.0: 125; RV64IZFINX-NEXT: fadd.s a0, a0, a1 126; RV64IZFINX-NEXT: sext.w a0, a0 127; RV64IZFINX-NEXT: ret 128 %1 = fadd float %a, %b 129 %2 = bitcast float %1 to i32 130 ret i32 %2 131} 132 133define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind { 134; RV64IF-LABEL: bcvt_f32_to_zext_i32: 135; RV64IF: # %bb.0: 136; RV64IF-NEXT: fadd.s fa5, fa0, fa1 137; RV64IF-NEXT: fmv.x.w a0, fa5 138; RV64IF-NEXT: slli a0, a0, 32 139; RV64IF-NEXT: srli a0, a0, 32 140; RV64IF-NEXT: ret 141; 142; RV64IZFINX-LABEL: bcvt_f32_to_zext_i32: 143; RV64IZFINX: # %bb.0: 144; RV64IZFINX-NEXT: fadd.s a0, a0, a1 145; RV64IZFINX-NEXT: slli a0, a0, 32 146; RV64IZFINX-NEXT: srli a0, a0, 32 147; RV64IZFINX-NEXT: ret 148 %1 = fadd float %a, %b 149 %2 = bitcast float %1 to i32 150 ret i32 %2 151} 152 153define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind { 154; RV64IF-LABEL: bcvt_i64_to_f32_via_i32: 155; RV64IF: # %bb.0: 156; RV64IF-NEXT: fmv.w.x fa5, a0 157; RV64IF-NEXT: fmv.w.x fa4, a1 158; RV64IF-NEXT: fadd.s fa0, fa5, fa4 159; RV64IF-NEXT: ret 160; 161; RV64IZFINX-LABEL: bcvt_i64_to_f32_via_i32: 162; RV64IZFINX: # %bb.0: 163; RV64IZFINX-NEXT: fadd.s a0, a0, a1 164; RV64IZFINX-NEXT: ret 165 %1 = trunc i64 %a to i32 166 %2 = trunc i64 %b to i32 167 %3 = bitcast i32 %1 to float 168 %4 = bitcast i32 %2 to float 169 %5 = fadd float %3, %4 170 ret float %5 171} 172 173define float @uitofp_aext_i32_to_f32(i32 %a) nounwind { 174; RV64IF-LABEL: uitofp_aext_i32_to_f32: 175; RV64IF: # %bb.0: 176; RV64IF-NEXT: fcvt.s.wu fa0, a0 177; RV64IF-NEXT: ret 178; 179; RV64IZFINX-LABEL: uitofp_aext_i32_to_f32: 180; RV64IZFINX: # %bb.0: 181; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 182; RV64IZFINX-NEXT: ret 183 %1 = uitofp i32 %a to float 184 ret float %1 185} 186 187define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind { 188; RV64IF-LABEL: uitofp_sext_i32_to_f32: 189; RV64IF: # %bb.0: 190; RV64IF-NEXT: fcvt.s.wu fa0, a0 191; RV64IF-NEXT: ret 192; 193; RV64IZFINX-LABEL: uitofp_sext_i32_to_f32: 194; RV64IZFINX: # %bb.0: 195; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 196; RV64IZFINX-NEXT: ret 197 %1 = uitofp i32 %a to float 198 ret float %1 199} 200 201define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { 202; RV64IF-LABEL: uitofp_zext_i32_to_f32: 203; RV64IF: # %bb.0: 204; RV64IF-NEXT: fcvt.s.wu fa0, a0 205; RV64IF-NEXT: ret 206; 207; RV64IZFINX-LABEL: uitofp_zext_i32_to_f32: 208; RV64IZFINX: # %bb.0: 209; RV64IZFINX-NEXT: fcvt.s.wu a0, a0 210; RV64IZFINX-NEXT: ret 211 %1 = uitofp i32 %a to float 212 ret float %1 213} 214 215define float @sitofp_aext_i32_to_f32(i32 %a) nounwind { 216; RV64IF-LABEL: sitofp_aext_i32_to_f32: 217; RV64IF: # %bb.0: 218; RV64IF-NEXT: fcvt.s.w fa0, a0 219; RV64IF-NEXT: ret 220; 221; RV64IZFINX-LABEL: sitofp_aext_i32_to_f32: 222; RV64IZFINX: # %bb.0: 223; RV64IZFINX-NEXT: fcvt.s.w a0, a0 224; RV64IZFINX-NEXT: ret 225 %1 = sitofp i32 %a to float 226 ret float %1 227} 228 229define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind { 230; RV64IF-LABEL: sitofp_sext_i32_to_f32: 231; RV64IF: # %bb.0: 232; RV64IF-NEXT: fcvt.s.w fa0, a0 233; RV64IF-NEXT: ret 234; 235; RV64IZFINX-LABEL: sitofp_sext_i32_to_f32: 236; RV64IZFINX: # %bb.0: 237; RV64IZFINX-NEXT: fcvt.s.w a0, a0 238; RV64IZFINX-NEXT: ret 239 %1 = sitofp i32 %a to float 240 ret float %1 241} 242 243define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind { 244; RV64IF-LABEL: sitofp_zext_i32_to_f32: 245; RV64IF: # %bb.0: 246; RV64IF-NEXT: fcvt.s.w fa0, a0 247; RV64IF-NEXT: ret 248; 249; RV64IZFINX-LABEL: sitofp_zext_i32_to_f32: 250; RV64IZFINX: # %bb.0: 251; RV64IZFINX-NEXT: fcvt.s.w a0, a0 252; RV64IZFINX-NEXT: ret 253 %1 = sitofp i32 %a to float 254 ret float %1 255} 256