xref: /llvm-project/llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll (revision a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zknh -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32ZKNH
4
5
6declare i32 @llvm.riscv.sha256sig0(i32);
7
8define i32 @sha256sig0_i32(i32 %a) nounwind {
9; RV32ZKNH-LABEL: sha256sig0_i32:
10; RV32ZKNH:       # %bb.0:
11; RV32ZKNH-NEXT:    sha256sig0 a0, a0
12; RV32ZKNH-NEXT:    ret
13    %val = call i32 @llvm.riscv.sha256sig0(i32 %a)
14    ret i32 %val
15}
16
17declare i32 @llvm.riscv.sha256sig1(i32);
18
19define i32 @sha256sig1_i32(i32 %a) nounwind {
20; RV32ZKNH-LABEL: sha256sig1_i32:
21; RV32ZKNH:       # %bb.0:
22; RV32ZKNH-NEXT:    sha256sig1 a0, a0
23; RV32ZKNH-NEXT:    ret
24    %val = call i32 @llvm.riscv.sha256sig1(i32 %a)
25    ret i32 %val
26}
27
28declare i32 @llvm.riscv.sha256sum0(i32);
29
30define i32 @sha256sum0_i32(i32 %a) nounwind {
31; RV32ZKNH-LABEL: sha256sum0_i32:
32; RV32ZKNH:       # %bb.0:
33; RV32ZKNH-NEXT:    sha256sum0 a0, a0
34; RV32ZKNH-NEXT:    ret
35    %val = call i32 @llvm.riscv.sha256sum0(i32 %a)
36    ret i32 %val
37}
38
39declare i32 @llvm.riscv.sha256sum1(i32);
40
41define i32 @sha256sum1_i32(i32 %a) nounwind {
42; RV32ZKNH-LABEL: sha256sum1_i32:
43; RV32ZKNH:       # %bb.0:
44; RV32ZKNH-NEXT:    sha256sum1 a0, a0
45; RV32ZKNH-NEXT:    ret
46    %val = call i32 @llvm.riscv.sha256sum1(i32 %a)
47    ret i32 %val
48}
49
50declare i32 @llvm.riscv.sha512sig0l(i32, i32);
51
52define i32 @sha512sig0l(i32 %a, i32 %b) nounwind {
53; RV32ZKNH-LABEL: sha512sig0l:
54; RV32ZKNH:       # %bb.0:
55; RV32ZKNH-NEXT:    sha512sig0l a0, a0, a1
56; RV32ZKNH-NEXT:    ret
57    %val = call i32 @llvm.riscv.sha512sig0l(i32 %a, i32 %b)
58    ret i32 %val
59}
60
61declare i32 @llvm.riscv.sha512sig0h(i32, i32);
62
63define i32 @sha512sig0h(i32 %a, i32 %b) nounwind {
64; RV32ZKNH-LABEL: sha512sig0h:
65; RV32ZKNH:       # %bb.0:
66; RV32ZKNH-NEXT:    sha512sig0h a0, a0, a1
67; RV32ZKNH-NEXT:    ret
68    %val = call i32 @llvm.riscv.sha512sig0h(i32 %a, i32 %b)
69    ret i32 %val
70}
71
72declare i32 @llvm.riscv.sha512sig1l(i32, i32);
73
74define i32 @sha512sig1l(i32 %a, i32 %b) nounwind {
75; RV32ZKNH-LABEL: sha512sig1l:
76; RV32ZKNH:       # %bb.0:
77; RV32ZKNH-NEXT:    sha512sig1l a0, a0, a1
78; RV32ZKNH-NEXT:    ret
79    %val = call i32 @llvm.riscv.sha512sig1l(i32 %a, i32 %b)
80    ret i32 %val
81}
82
83declare i32 @llvm.riscv.sha512sig1h(i32, i32);
84
85define i32 @sha512sig1h(i32 %a, i32 %b) nounwind {
86; RV32ZKNH-LABEL: sha512sig1h:
87; RV32ZKNH:       # %bb.0:
88; RV32ZKNH-NEXT:    sha512sig1h a0, a0, a1
89; RV32ZKNH-NEXT:    ret
90    %val = call i32 @llvm.riscv.sha512sig1h(i32 %a, i32 %b)
91    ret i32 %val
92}
93
94declare i32 @llvm.riscv.sha512sum0r(i32, i32);
95
96define i32 @sha512sum0r(i32 %a, i32 %b) nounwind {
97; RV32ZKNH-LABEL: sha512sum0r:
98; RV32ZKNH:       # %bb.0:
99; RV32ZKNH-NEXT:    sha512sum0r a0, a0, a1
100; RV32ZKNH-NEXT:    ret
101    %val = call i32 @llvm.riscv.sha512sum0r(i32 %a, i32 %b)
102    ret i32 %val
103}
104
105declare i32 @llvm.riscv.sha512sum1r(i32, i32);
106
107define i32 @sha512sum1r(i32 %a, i32 %b) nounwind {
108; RV32ZKNH-LABEL: sha512sum1r:
109; RV32ZKNH:       # %bb.0:
110; RV32ZKNH-NEXT:    sha512sum1r a0, a0, a1
111; RV32ZKNH-NEXT:    ret
112    %val = call i32 @llvm.riscv.sha512sum1r(i32 %a, i32 %b)
113    ret i32 %val
114}
115