1f78d932cSLevy Hsu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*33d008b1SAlex Bradbury; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \ 3e3560270SCraig Topper; RUN: | FileCheck %s -check-prefix=RV32ZBC 4f78d932cSLevy Hsu 5f78d932cSLevy Hsudeclare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 6f78d932cSLevy Hsu 7f78d932cSLevy Hsudefine i32 @clmul32r(i32 %a, i32 %b) nounwind { 8e3560270SCraig Topper; RV32ZBC-LABEL: clmul32r: 9e3560270SCraig Topper; RV32ZBC: # %bb.0: 10e3560270SCraig Topper; RV32ZBC-NEXT: clmulr a0, a0, a1 11e3560270SCraig Topper; RV32ZBC-NEXT: ret 12f78d932cSLevy Hsu %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 13f78d932cSLevy Hsu ret i32 %tmp 14f78d932cSLevy Hsu} 15