1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32ZBC 4 5declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 6 7define i32 @clmul32r(i32 %a, i32 %b) nounwind { 8; RV32ZBC-LABEL: clmul32r: 9; RV32ZBC: # %bb.0: 10; RV32ZBC-NEXT: clmulr a0, a0, a1 11; RV32ZBC-NEXT: ret 12 %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b) 13 ret i32 %tmp 14} 15