1944adbf2SLevy Hsu; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 233d008b1SAlex Bradbury; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \ 3a2556bf4SCraig Topper; RUN: | FileCheck %s -check-prefix=RV32ZBB 4944adbf2SLevy Hsu 5944adbf2SLevy Hsudeclare i32 @llvm.riscv.orc.b.i32(i32) 6944adbf2SLevy Hsu 7944adbf2SLevy Hsudefine i32 @orcb(i32 %a) nounwind { 8a2556bf4SCraig Topper; RV32ZBB-LABEL: orcb: 9a2556bf4SCraig Topper; RV32ZBB: # %bb.0: 10a2556bf4SCraig Topper; RV32ZBB-NEXT: orc.b a0, a0 11a2556bf4SCraig Topper; RV32ZBB-NEXT: ret 12944adbf2SLevy Hsu %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) 13944adbf2SLevy Hsu ret i32 %tmp 14944adbf2SLevy Hsu} 15*01203918SCraig Topper 16*01203918SCraig Topper; Second and+or are redundant with the first, make sure we remove it. 17*01203918SCraig Topperdefine i32 @orcb_knownbits(i32 %a) nounwind { 18*01203918SCraig Topper; RV32ZBB-LABEL: orcb_knownbits: 19*01203918SCraig Topper; RV32ZBB: # %bb.0: 20*01203918SCraig Topper; RV32ZBB-NEXT: lui a1, 1044480 21*01203918SCraig Topper; RV32ZBB-NEXT: and a0, a0, a1 22*01203918SCraig Topper; RV32ZBB-NEXT: lui a1, 2048 23*01203918SCraig Topper; RV32ZBB-NEXT: addi a1, a1, 1 24*01203918SCraig Topper; RV32ZBB-NEXT: or a0, a0, a1 25*01203918SCraig Topper; RV32ZBB-NEXT: orc.b a0, a0 26*01203918SCraig Topper; RV32ZBB-NEXT: ret 27*01203918SCraig Topper %tmp = and i32 %a, 4278190080 ; 0xFF000000 28*01203918SCraig Topper %tmp2 = or i32 %tmp, 8388609 ; 0x800001 29*01203918SCraig Topper %tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2) 30*01203918SCraig Topper %tmp4 = and i32 %tmp3, 4278190080 ; 0xFF000000 31*01203918SCraig Topper %tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF 32*01203918SCraig Topper ret i32 %tmp5 33*01203918SCraig Topper} 34