1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32ZBB 4 5declare i32 @llvm.riscv.orc.b.i32(i32) 6 7define i32 @orcb(i32 %a) nounwind { 8; RV32ZBB-LABEL: orcb: 9; RV32ZBB: # %bb.0: 10; RV32ZBB-NEXT: orc.b a0, a0 11; RV32ZBB-NEXT: ret 12 %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) 13 ret i32 %tmp 14} 15 16; Second and+or are redundant with the first, make sure we remove it. 17define i32 @orcb_knownbits(i32 %a) nounwind { 18; RV32ZBB-LABEL: orcb_knownbits: 19; RV32ZBB: # %bb.0: 20; RV32ZBB-NEXT: lui a1, 1044480 21; RV32ZBB-NEXT: and a0, a0, a1 22; RV32ZBB-NEXT: lui a1, 2048 23; RV32ZBB-NEXT: addi a1, a1, 1 24; RV32ZBB-NEXT: or a0, a0, a1 25; RV32ZBB-NEXT: orc.b a0, a0 26; RV32ZBB-NEXT: ret 27 %tmp = and i32 %a, 4278190080 ; 0xFF000000 28 %tmp2 = or i32 %tmp, 8388609 ; 0x800001 29 %tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2) 30 %tmp4 = and i32 %tmp3, 4278190080 ; 0xFF000000 31 %tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF 32 ret i32 %tmp5 33} 34