1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64I %s 6 7; This file provides a simple test check of half operations for 8; RV32I and RV64I. This is primarily intended to ensure that custom 9; legalisation or DAG combines aren't incorrectly triggered when the Zfh 10; extension isn't enabled. 11 12define half @half_test(half %a, half %b) nounwind { 13; RV32I-LABEL: half_test: 14; RV32I: # %bb.0: 15; RV32I-NEXT: addi sp, sp, -16 16; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 17; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill 18; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill 19; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill 20; RV32I-NEXT: mv s0, a1 21; RV32I-NEXT: lui a1, 16 22; RV32I-NEXT: addi s2, a1, -1 23; RV32I-NEXT: and a0, a0, s2 24; RV32I-NEXT: call __extendhfsf2 25; RV32I-NEXT: mv s1, a0 26; RV32I-NEXT: and a0, s0, s2 27; RV32I-NEXT: call __extendhfsf2 28; RV32I-NEXT: mv s0, a0 29; RV32I-NEXT: mv a0, s1 30; RV32I-NEXT: mv a1, s0 31; RV32I-NEXT: call __addsf3 32; RV32I-NEXT: call __truncsfhf2 33; RV32I-NEXT: and a0, a0, s2 34; RV32I-NEXT: call __extendhfsf2 35; RV32I-NEXT: mv a1, s0 36; RV32I-NEXT: call __divsf3 37; RV32I-NEXT: call __truncsfhf2 38; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 39; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload 40; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload 41; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload 42; RV32I-NEXT: addi sp, sp, 16 43; RV32I-NEXT: ret 44; 45; RV64I-LABEL: half_test: 46; RV64I: # %bb.0: 47; RV64I-NEXT: addi sp, sp, -32 48; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 49; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 50; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 51; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 52; RV64I-NEXT: mv s0, a1 53; RV64I-NEXT: lui a1, 16 54; RV64I-NEXT: addiw s2, a1, -1 55; RV64I-NEXT: and a0, a0, s2 56; RV64I-NEXT: call __extendhfsf2 57; RV64I-NEXT: mv s1, a0 58; RV64I-NEXT: and a0, s0, s2 59; RV64I-NEXT: call __extendhfsf2 60; RV64I-NEXT: mv s0, a0 61; RV64I-NEXT: mv a0, s1 62; RV64I-NEXT: mv a1, s0 63; RV64I-NEXT: call __addsf3 64; RV64I-NEXT: call __truncsfhf2 65; RV64I-NEXT: and a0, a0, s2 66; RV64I-NEXT: call __extendhfsf2 67; RV64I-NEXT: mv a1, s0 68; RV64I-NEXT: call __divsf3 69; RV64I-NEXT: call __truncsfhf2 70; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 71; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 72; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 73; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 74; RV64I-NEXT: addi sp, sp, 32 75; RV64I-NEXT: ret 76 %1 = fadd half %a, %b 77 %2 = fdiv half %1, %b 78 ret half %2 79} 80