1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh \ 3; RUN: -enable-subreg-liveness=false < %s | FileCheck %s 4; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh < %s \ 5; RUN: -enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS 6 7; This testcase failed to compile after 8; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted. 9 10; FIXME: The failure does not reproduce with -stop-before=greedy 11; output MIR with -start-before=greedy 12 13define void @last_chance_recoloring_failure() { 14; CHECK-LABEL: last_chance_recoloring_failure: 15; CHECK: # %bb.0: # %entry 16; CHECK-NEXT: addi sp, sp, -32 17; CHECK-NEXT: .cfi_def_cfa_offset 32 18; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 19; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 20; CHECK-NEXT: .cfi_offset ra, -8 21; CHECK-NEXT: .cfi_offset s0, -16 22; CHECK-NEXT: csrr a0, vlenb 23; CHECK-NEXT: slli a0, a0, 4 24; CHECK-NEXT: sub sp, sp, a0 25; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb 26; CHECK-NEXT: li a0, 55 27; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma 28; CHECK-NEXT: vmclr.m v0 29; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 30; CHECK-NEXT: vloxseg2ei32.v v16, (a1), v8 31; CHECK-NEXT: csrr a0, vlenb 32; CHECK-NEXT: slli a0, a0, 3 33; CHECK-NEXT: add a0, sp, a0 34; CHECK-NEXT: addi a0, a0, 16 35; CHECK-NEXT: csrr a1, vlenb 36; CHECK-NEXT: slli a1, a1, 2 37; CHECK-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill 38; CHECK-NEXT: add a0, a0, a1 39; CHECK-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill 40; CHECK-NEXT: li s0, 36 41; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma 42; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t 43; CHECK-NEXT: addi a0, sp, 16 44; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill 45; CHECK-NEXT: call func 46; CHECK-NEXT: csrr a0, vlenb 47; CHECK-NEXT: slli a0, a0, 3 48; CHECK-NEXT: add a0, sp, a0 49; CHECK-NEXT: addi a0, a0, 16 50; CHECK-NEXT: csrr a1, vlenb 51; CHECK-NEXT: slli a1, a1, 2 52; CHECK-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload 53; CHECK-NEXT: add a0, a0, a1 54; CHECK-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload 55; CHECK-NEXT: addi a0, sp, 16 56; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload 57; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma 58; CHECK-NEXT: vfwsub.wv v8, v24, v16 59; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu 60; CHECK-NEXT: vfdiv.vv v8, v24, v8, v0.t 61; CHECK-NEXT: vse32.v v8, (a0) 62; CHECK-NEXT: csrr a0, vlenb 63; CHECK-NEXT: slli a0, a0, 4 64; CHECK-NEXT: add sp, sp, a0 65; CHECK-NEXT: .cfi_def_cfa sp, 32 66; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 67; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 68; CHECK-NEXT: .cfi_restore ra 69; CHECK-NEXT: .cfi_restore s0 70; CHECK-NEXT: addi sp, sp, 32 71; CHECK-NEXT: .cfi_def_cfa_offset 0 72; CHECK-NEXT: ret 73; 74; SUBREGLIVENESS-LABEL: last_chance_recoloring_failure: 75; SUBREGLIVENESS: # %bb.0: # %entry 76; SUBREGLIVENESS-NEXT: addi sp, sp, -32 77; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32 78; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 79; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 80; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8 81; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16 82; SUBREGLIVENESS-NEXT: csrr a0, vlenb 83; SUBREGLIVENESS-NEXT: slli a0, a0, 4 84; SUBREGLIVENESS-NEXT: sub sp, sp, a0 85; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb 86; SUBREGLIVENESS-NEXT: li a0, 55 87; SUBREGLIVENESS-NEXT: vsetvli a2, zero, e8, m2, ta, ma 88; SUBREGLIVENESS-NEXT: vmclr.m v0 89; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma 90; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v16, (a1), v8 91; SUBREGLIVENESS-NEXT: csrr a0, vlenb 92; SUBREGLIVENESS-NEXT: slli a0, a0, 3 93; SUBREGLIVENESS-NEXT: add a0, sp, a0 94; SUBREGLIVENESS-NEXT: addi a0, a0, 16 95; SUBREGLIVENESS-NEXT: csrr a1, vlenb 96; SUBREGLIVENESS-NEXT: slli a1, a1, 2 97; SUBREGLIVENESS-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill 98; SUBREGLIVENESS-NEXT: add a0, a0, a1 99; SUBREGLIVENESS-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill 100; SUBREGLIVENESS-NEXT: li s0, 36 101; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma 102; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t 103; SUBREGLIVENESS-NEXT: addi a0, sp, 16 104; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill 105; SUBREGLIVENESS-NEXT: call func 106; SUBREGLIVENESS-NEXT: csrr a0, vlenb 107; SUBREGLIVENESS-NEXT: slli a0, a0, 3 108; SUBREGLIVENESS-NEXT: add a0, sp, a0 109; SUBREGLIVENESS-NEXT: addi a0, a0, 16 110; SUBREGLIVENESS-NEXT: csrr a1, vlenb 111; SUBREGLIVENESS-NEXT: slli a1, a1, 2 112; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload 113; SUBREGLIVENESS-NEXT: add a0, a0, a1 114; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload 115; SUBREGLIVENESS-NEXT: addi a0, sp, 16 116; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload 117; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma 118; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v16 119; SUBREGLIVENESS-NEXT: vsetvli zero, zero, e32, m8, tu, mu 120; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t 121; SUBREGLIVENESS-NEXT: vse32.v v8, (a0) 122; SUBREGLIVENESS-NEXT: csrr a0, vlenb 123; SUBREGLIVENESS-NEXT: slli a0, a0, 4 124; SUBREGLIVENESS-NEXT: add sp, sp, a0 125; SUBREGLIVENESS-NEXT: .cfi_def_cfa sp, 32 126; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 127; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 128; SUBREGLIVENESS-NEXT: .cfi_restore ra 129; SUBREGLIVENESS-NEXT: .cfi_restore s0 130; SUBREGLIVENESS-NEXT: addi sp, sp, 32 131; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 0 132; SUBREGLIVENESS-NEXT: ret 133entry: 134 %i = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) undef, ptr nonnull poison, <vscale x 16 x i32> poison, i64 55, i64 4) 135 %i1 = tail call <vscale x 16 x half> @llvm.riscv.tuple.extract.v16f16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %i, i32 0) 136 %i2 = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> poison, <vscale x 16 x half> poison, <vscale x 16 x i1> zeroinitializer, i64 7, i64 36, i64 0) 137 call void @func() 138 %i3 = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0) 139 %i4 = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %i2, <vscale x 16 x half> %i1, i64 7, i64 36) 140 %i5 = call <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> %i3, <vscale x 16 x i16> %i3, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison, i64 32, i64 0) 141 %i6 = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> %i4, <vscale x 16 x float> %i2, <vscale x 16 x float> poison, <vscale x 16 x i1> poison, i64 7, i64 36, i64 0) 142 call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %i6, ptr nonnull poison, i64 36) 143 ret void 144} 145 146declare void @func() 147declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.nxv16f16.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr nocapture, <vscale x 16 x i32>, i64, i64) 148declare <vscale x 16 x half> @llvm.riscv.tuple.extract.v16f16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32) 149declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64, i64, i64 immarg) 150declare <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg) 151declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x half>, i64, i64) 152declare <vscale x 16 x i16> @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i64, i64 immarg) 153declare <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64, i64 immarg) 154declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, ptr nocapture, i64) #3 155