1*557bf383SYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2*557bf383SYingwei Zheng; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s 3*557bf383SYingwei Zheng 4*557bf383SYingwei Zhengdefine i32 @pr90730(i32 %x, i1 %y, ptr %p) { 5*557bf383SYingwei Zheng; CHECK-LABEL: pr90730: 6*557bf383SYingwei Zheng; CHECK: # %bb.0: # %entry 7*557bf383SYingwei Zheng; CHECK-NEXT: lui a1, 8 8*557bf383SYingwei Zheng; CHECK-NEXT: addiw a1, a1, -960 9*557bf383SYingwei Zheng; CHECK-NEXT: andn a0, a1, a0 10*557bf383SYingwei Zheng; CHECK-NEXT: sw zero, 0(a2) 11*557bf383SYingwei Zheng; CHECK-NEXT: ret 12*557bf383SYingwei Zhengentry: 13*557bf383SYingwei Zheng %ext = zext i1 %y to i32 14*557bf383SYingwei Zheng %xor1 = xor i32 %ext, 31817 15*557bf383SYingwei Zheng %and1 = and i32 %xor1, %x 16*557bf383SYingwei Zheng store i32 %and1, ptr %p, align 4 17*557bf383SYingwei Zheng %v = load i32, ptr %p, align 4 18*557bf383SYingwei Zheng %and2 = and i32 %v, 31808 19*557bf383SYingwei Zheng %xor2 = xor i32 %and2, 31808 20*557bf383SYingwei Zheng store i32 0, ptr %p, align 4 21*557bf383SYingwei Zheng ret i32 %xor2 22*557bf383SYingwei Zheng} 23