xref: /llvm-project/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll (revision 6e7312bda60249c25e2ae9078d9f70bc2a65838c)

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK-NOZBB
; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK-ZBB

; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more
; poisonous AND operation).
define i1 @pr84653(i32 %x) {
; CHECK-NOZBB-LABEL: pr84653:
; CHECK-NOZBB:       # %bb.0:
; CHECK-NOZBB-NEXT:    sext.w a1, a0
; CHECK-NOZBB-NEXT:    lui a2, 524288
; CHECK-NOZBB-NEXT:    sgtz a3, a1
; CHECK-NOZBB-NEXT:    addi a2, a2, -1
; CHECK-NOZBB-NEXT:    xor a0, a0, a2
; CHECK-NOZBB-NEXT:    sext.w a0, a0
; CHECK-NOZBB-NEXT:    slt a0, a0, a1
; CHECK-NOZBB-NEXT:    and a0, a3, a0
; CHECK-NOZBB-NEXT:    ret
;
; CHECK-ZBB-LABEL: pr84653:
; CHECK-ZBB:       # %bb.0:
; CHECK-ZBB-NEXT:    sext.w a1, a0
; CHECK-ZBB-NEXT:    lui a2, 524288
; CHECK-ZBB-NEXT:    xnor a0, a0, a2
; CHECK-ZBB-NEXT:    sext.w a0, a0
; CHECK-ZBB-NEXT:    max a0, a0, zero
; CHECK-ZBB-NEXT:    slt a0, a0, a1
; CHECK-ZBB-NEXT:    ret
  %cmp1 = icmp sgt i32 %x, 0
  %sub = sub nsw i32 2147483647, %x  ; 0x7fffffff
  %cmp2 = icmp sgt i32 %x, %sub
  %r = select i1 %cmp1, i1 %cmp2, i1 false
  ret i1 %r
}

; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more
; poisonous AND operation).
define i1 @pr85190(i64 %a) {
; CHECK-NOZBB-LABEL: pr85190:
; CHECK-NOZBB:       # %bb.0:
; CHECK-NOZBB-NEXT:    ori a1, a0, 7
; CHECK-NOZBB-NEXT:    slti a2, a0, 0
; CHECK-NOZBB-NEXT:    li a3, -1
; CHECK-NOZBB-NEXT:    slli a3, a3, 63
; CHECK-NOZBB-NEXT:    sub a3, a3, a1
; CHECK-NOZBB-NEXT:    slt a0, a0, a3
; CHECK-NOZBB-NEXT:    and a0, a2, a0
; CHECK-NOZBB-NEXT:    ret
;
; CHECK-ZBB-LABEL: pr85190:
; CHECK-ZBB:       # %bb.0:
; CHECK-ZBB-NEXT:    ori a1, a0, 7
; CHECK-ZBB-NEXT:    li a2, -1
; CHECK-ZBB-NEXT:    slli a2, a2, 63
; CHECK-ZBB-NEXT:    sub a2, a2, a1
; CHECK-ZBB-NEXT:    min a1, a2, zero
; CHECK-ZBB-NEXT:    slt a0, a0, a1
; CHECK-ZBB-NEXT:    ret
  %or = or i64 %a, 7
  %cmp1 = icmp slt i64 %a, 0
  %sub = sub nsw i64 -9223372036854775808, %or  ; 0x8000000000000000
  %cmp2 = icmp sgt i64 %sub, %a
  %res = select i1 %cmp1, i1 %cmp2, i1 false
  ret i1 %res
}

define i1 @select_to_or(i32 %x) {
; CHECK-NOZBB-LABEL: select_to_or:
; CHECK-NOZBB:       # %bb.0:
; CHECK-NOZBB-NEXT:    sext.w a1, a0
; CHECK-NOZBB-NEXT:    lui a2, 524288
; CHECK-NOZBB-NEXT:    sgtz a3, a1
; CHECK-NOZBB-NEXT:    addi a2, a2, -1
; CHECK-NOZBB-NEXT:    xor a0, a0, a2
; CHECK-NOZBB-NEXT:    sext.w a0, a0
; CHECK-NOZBB-NEXT:    slt a0, a0, a1
; CHECK-NOZBB-NEXT:    or a0, a3, a0
; CHECK-NOZBB-NEXT:    ret
;
; CHECK-ZBB-LABEL: select_to_or:
; CHECK-ZBB:       # %bb.0:
; CHECK-ZBB-NEXT:    sext.w a1, a0
; CHECK-ZBB-NEXT:    lui a2, 524288
; CHECK-ZBB-NEXT:    xnor a0, a0, a2
; CHECK-ZBB-NEXT:    sext.w a0, a0
; CHECK-ZBB-NEXT:    min a0, a0, zero
; CHECK-ZBB-NEXT:    slt a0, a0, a1
; CHECK-ZBB-NEXT:    ret
  %cmp1 = icmp sgt i32 %x, 0
  %sub = sub nsw i32 2147483647, %x  ; 0x7fffffff
  %cmp2 = icmp sgt i32 %x, %sub
  %r = select i1 %cmp1, i1 true, i1 %cmp2
  ret i1 %r
}