1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK-NOZBB 3; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK-ZBB 4 5; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more 6; poisonous AND operation). 7define i1 @pr84653(i32 %x) { 8; CHECK-NOZBB-LABEL: pr84653: 9; CHECK-NOZBB: # %bb.0: 10; CHECK-NOZBB-NEXT: sext.w a1, a0 11; CHECK-NOZBB-NEXT: lui a2, 524288 12; CHECK-NOZBB-NEXT: sgtz a3, a1 13; CHECK-NOZBB-NEXT: addi a2, a2, -1 14; CHECK-NOZBB-NEXT: xor a0, a0, a2 15; CHECK-NOZBB-NEXT: sext.w a0, a0 16; CHECK-NOZBB-NEXT: slt a0, a0, a1 17; CHECK-NOZBB-NEXT: and a0, a3, a0 18; CHECK-NOZBB-NEXT: ret 19; 20; CHECK-ZBB-LABEL: pr84653: 21; CHECK-ZBB: # %bb.0: 22; CHECK-ZBB-NEXT: sext.w a1, a0 23; CHECK-ZBB-NEXT: lui a2, 524288 24; CHECK-ZBB-NEXT: xnor a0, a0, a2 25; CHECK-ZBB-NEXT: sext.w a0, a0 26; CHECK-ZBB-NEXT: max a0, a0, zero 27; CHECK-ZBB-NEXT: slt a0, a0, a1 28; CHECK-ZBB-NEXT: ret 29 %cmp1 = icmp sgt i32 %x, 0 30 %sub = sub nsw i32 2147483647, %x ; 0x7fffffff 31 %cmp2 = icmp sgt i32 %x, %sub 32 %r = select i1 %cmp1, i1 %cmp2, i1 false 33 ret i1 %r 34} 35 36; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more 37; poisonous AND operation). 38define i1 @pr85190(i64 %a) { 39; CHECK-NOZBB-LABEL: pr85190: 40; CHECK-NOZBB: # %bb.0: 41; CHECK-NOZBB-NEXT: ori a1, a0, 7 42; CHECK-NOZBB-NEXT: slti a2, a0, 0 43; CHECK-NOZBB-NEXT: li a3, -1 44; CHECK-NOZBB-NEXT: slli a3, a3, 63 45; CHECK-NOZBB-NEXT: sub a3, a3, a1 46; CHECK-NOZBB-NEXT: slt a0, a0, a3 47; CHECK-NOZBB-NEXT: and a0, a2, a0 48; CHECK-NOZBB-NEXT: ret 49; 50; CHECK-ZBB-LABEL: pr85190: 51; CHECK-ZBB: # %bb.0: 52; CHECK-ZBB-NEXT: ori a1, a0, 7 53; CHECK-ZBB-NEXT: li a2, -1 54; CHECK-ZBB-NEXT: slli a2, a2, 63 55; CHECK-ZBB-NEXT: sub a2, a2, a1 56; CHECK-ZBB-NEXT: min a1, a2, zero 57; CHECK-ZBB-NEXT: slt a0, a0, a1 58; CHECK-ZBB-NEXT: ret 59 %or = or i64 %a, 7 60 %cmp1 = icmp slt i64 %a, 0 61 %sub = sub nsw i64 -9223372036854775808, %or ; 0x8000000000000000 62 %cmp2 = icmp sgt i64 %sub, %a 63 %res = select i1 %cmp1, i1 %cmp2, i1 false 64 ret i1 %res 65} 66 67define i1 @select_to_or(i32 %x) { 68; CHECK-NOZBB-LABEL: select_to_or: 69; CHECK-NOZBB: # %bb.0: 70; CHECK-NOZBB-NEXT: sext.w a1, a0 71; CHECK-NOZBB-NEXT: lui a2, 524288 72; CHECK-NOZBB-NEXT: sgtz a3, a1 73; CHECK-NOZBB-NEXT: addi a2, a2, -1 74; CHECK-NOZBB-NEXT: xor a0, a0, a2 75; CHECK-NOZBB-NEXT: sext.w a0, a0 76; CHECK-NOZBB-NEXT: slt a0, a0, a1 77; CHECK-NOZBB-NEXT: or a0, a3, a0 78; CHECK-NOZBB-NEXT: ret 79; 80; CHECK-ZBB-LABEL: select_to_or: 81; CHECK-ZBB: # %bb.0: 82; CHECK-ZBB-NEXT: sext.w a1, a0 83; CHECK-ZBB-NEXT: lui a2, 524288 84; CHECK-ZBB-NEXT: xnor a0, a0, a2 85; CHECK-ZBB-NEXT: sext.w a0, a0 86; CHECK-ZBB-NEXT: min a0, a0, zero 87; CHECK-ZBB-NEXT: slt a0, a0, a1 88; CHECK-ZBB-NEXT: ret 89 %cmp1 = icmp sgt i32 %x, 0 90 %sub = sub nsw i32 2147483647, %x ; 0x7fffffff 91 %cmp2 = icmp sgt i32 %x, %sub 92 %r = select i1 %cmp1, i1 true, i1 %cmp2 93 ret i1 %r 94} 95