1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 2# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s 3 4--- 5name: fcvtmod_w_d 6tracksRegLiveness: true 7body: | 8 bb.0.entry: 9 liveins: $x10 10 11 ; CHECK-LABEL: name: fcvtmod_w_d 12 ; CHECK: liveins: $x10 13 ; CHECK-NEXT: {{ $}} 14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10 15 ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1 16 ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]] 17 ; CHECK-NEXT: PseudoRET 18 %0:fpr64 = COPY $x10 19 20 %1:gpr = nofpexcept FCVTMOD_W_D %0, 1 21 %2:gpr = ADDIW %1, 0 22 $x10 = COPY %2 23 PseudoRET 24... 25 26--- 27name: physreg 28tracksRegLiveness: true 29body: | 30 bb.0.entry: 31 liveins: $x10, $x11 32 33 ; CHECK-LABEL: name: physreg 34 ; CHECK: liveins: $x10, $x11 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 37 ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 38 ; CHECK-NEXT: $x10 = COPY [[ADDIW]] 39 ; CHECK-NEXT: PseudoRET 40 %0:gpr = COPY $x10 41 %1:gpr = ADDIW %0, 0 42 $x10 = COPY %1 43 PseudoRET 44... 45--- 46 name: vfirst 47 tracksRegLiveness: true 48 body: | 49 bb.0.entry: 50 liveins: $x10, $v8 51 52 ; CHECK-LABEL: name: vfirst 53 ; CHECK: liveins: $x10, $v8 54 ; CHECK-NEXT: {{ $}} 55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 56 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 57 ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ 58 ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]] 59 ; CHECK-NEXT: PseudoRET 60 %0:vr = COPY $v8 61 %1:gprnox0 = COPY $x10 62 63 %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0 64 %3:gpr = ADDIW %2, 0 65 $x11 = COPY %3 66 PseudoRET 67... 68--- 69 name: vcpop 70 tracksRegLiveness: true 71 body: | 72 bb.0.entry: 73 liveins: $x10, $v8 74 75 ; CHECK-LABEL: name: vcpop 76 ; CHECK: liveins: $x10, $v8 77 ; CHECK-NEXT: {{ $}} 78 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 79 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 80 ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ 81 ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]] 82 ; CHECK-NEXT: PseudoRET 83 %0:vr = COPY $v8 84 %1:gprnox0 = COPY $x10 85 86 %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0 87 %3:gpr = ADDIW %2, 0 88 $x11 = COPY %3 89 PseudoRET 90... 91--- 92 name: th_lwd 93 tracksRegLiveness: true 94 body: | 95 bb.0.entry: 96 liveins: $x10 97 ; CHECK-LABEL: name: th_lwd 98 ; CHECK: liveins: $x10 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 101 ; CHECK-NEXT: early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD [[COPY]], 2, 3 102 ; CHECK-NEXT: $x10 = COPY %1 103 ; CHECK-NEXT: $x11 = COPY %2 104 ; CHECK-NEXT: PseudoRET 105 %0:gpr = COPY $x10 106 early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD %0, 2, 3 107 %3:gpr = ADDIW %1, 0 108 %4:gpr = ADDIW %2, 0 109 $x10 = COPY %3 110 $x11 = COPY %4 111 PseudoRET 112... 113 114