xref: /llvm-project/llvm/test/CodeGen/RISCV/nest-register.ll (revision eabaee0c59110d0e11b33a69db54ccda526b35fd)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7; Tests that the 'nest' parameter attribute causes the relevant parameter to be
8; passed in the right register.
9
10define ptr @nest_receiver(ptr nest %arg) nounwind {
11; RV32I-LABEL: nest_receiver:
12; RV32I:       # %bb.0:
13; RV32I-NEXT:    mv a0, t2
14; RV32I-NEXT:    ret
15;
16; RV64I-LABEL: nest_receiver:
17; RV64I:       # %bb.0:
18; RV64I-NEXT:    mv a0, t2
19; RV64I-NEXT:    ret
20  ret ptr %arg
21}
22
23define ptr @nest_caller(ptr %arg) nounwind {
24; RV32I-LABEL: nest_caller:
25; RV32I:       # %bb.0:
26; RV32I-NEXT:    addi sp, sp, -16
27; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
28; RV32I-NEXT:    mv t2, a0
29; RV32I-NEXT:    call nest_receiver
30; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
31; RV32I-NEXT:    addi sp, sp, 16
32; RV32I-NEXT:    ret
33;
34; RV64I-LABEL: nest_caller:
35; RV64I:       # %bb.0:
36; RV64I-NEXT:    addi sp, sp, -16
37; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
38; RV64I-NEXT:    mv t2, a0
39; RV64I-NEXT:    call nest_receiver
40; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
41; RV64I-NEXT:    addi sp, sp, 16
42; RV64I-NEXT:    ret
43  %result = call ptr @nest_receiver(ptr nest %arg)
44  ret ptr %result
45}
46