xref: /llvm-project/llvm/test/CodeGen/RISCV/narrow-shl-cst.ll (revision a2b5b584a576b253165e17e32d8c5627021ac881) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
4
5define signext i32 @test1(i32 signext %x) nounwind {
6; RV32-LABEL: test1:
7; RV32:       # %bb.0:
8; RV32-NEXT:    ori a0, a0, 31
9; RV32-NEXT:    slli a0, a0, 10
10; RV32-NEXT:    ret
11;
12; RV64-LABEL: test1:
13; RV64:       # %bb.0:
14; RV64-NEXT:    ori a0, a0, 31
15; RV64-NEXT:    slliw a0, a0, 10
16; RV64-NEXT:    ret
17  %or = shl i32 %x, 10
18  %shl = or i32 %or, 31744
19  ret i32 %shl
20}
21
22define signext i32 @test2(i32 signext %x) nounwind {
23; RV32-LABEL: test2:
24; RV32:       # %bb.0:
25; RV32-NEXT:    xori a0, a0, 31
26; RV32-NEXT:    slli a0, a0, 10
27; RV32-NEXT:    ret
28;
29; RV64-LABEL: test2:
30; RV64:       # %bb.0:
31; RV64-NEXT:    xori a0, a0, 31
32; RV64-NEXT:    slliw a0, a0, 10
33; RV64-NEXT:    ret
34  %xor = shl i32 %x, 10
35  %shl = xor i32 %xor, 31744
36  ret i32 %shl
37}
38
39define i64 @test3(i64 %x) nounwind {
40; RV32-LABEL: test3:
41; RV32:       # %bb.0:
42; RV32-NEXT:    andi a1, a0, 241
43; RV32-NEXT:    slli a1, a1, 8
44; RV32-NEXT:    li a0, 0
45; RV32-NEXT:    ret
46;
47; RV64-LABEL: test3:
48; RV64:       # %bb.0:
49; RV64-NEXT:    andi a0, a0, 241
50; RV64-NEXT:    slli a0, a0, 40
51; RV64-NEXT:    ret
52  %and = shl i64 %x, 40
53  %shl = and i64 %and, 264982302294016
54  ret i64 %shl
55}
56
57define i64 @test4(i64 %x) nounwind {
58; RV32-LABEL: test4:
59; RV32:       # %bb.0:
60; RV32-NEXT:    ori a1, a0, 241
61; RV32-NEXT:    slli a1, a1, 8
62; RV32-NEXT:    li a0, 0
63; RV32-NEXT:    ret
64;
65; RV64-LABEL: test4:
66; RV64:       # %bb.0:
67; RV64-NEXT:    ori a0, a0, 241
68; RV64-NEXT:    slli a0, a0, 40
69; RV64-NEXT:    ret
70  %or = shl i64 %x, 40
71  %shl = or i64 %or, 264982302294016
72  ret i64 %shl
73}
74
75define i64 @test5(i64 %x) nounwind {
76; RV32-LABEL: test5:
77; RV32:       # %bb.0:
78; RV32-NEXT:    ori a1, a0, 31
79; RV32-NEXT:    slli a1, a1, 8
80; RV32-NEXT:    li a0, 0
81; RV32-NEXT:    ret
82;
83; RV64-LABEL: test5:
84; RV64:       # %bb.0:
85; RV64-NEXT:    ori a0, a0, 31
86; RV64-NEXT:    slli a0, a0, 40
87; RV64-NEXT:    ret
88  %or = shl i64 %x, 40
89  %shl = or i64 %or, 34084860461056
90  ret i64 %shl
91}
92
93define i64 @test6(i64 %x) nounwind {
94; RV32-LABEL: test6:
95; RV32:       # %bb.0:
96; RV32-NEXT:    xori a1, a0, 241
97; RV32-NEXT:    slli a1, a1, 8
98; RV32-NEXT:    li a0, 0
99; RV32-NEXT:    ret
100;
101; RV64-LABEL: test6:
102; RV64:       # %bb.0:
103; RV64-NEXT:    xori a0, a0, 241
104; RV64-NEXT:    slli a0, a0, 40
105; RV64-NEXT:    ret
106  %xor = shl i64 %x, 40
107  %shl = xor i64 %xor, 264982302294016
108  ret i64 %shl
109}
110
111define i64 @test7(i64 %x) nounwind {
112; RV32-LABEL: test7:
113; RV32:       # %bb.0:
114; RV32-NEXT:    xori a1, a0, 31
115; RV32-NEXT:    slli a1, a1, 8
116; RV32-NEXT:    li a0, 0
117; RV32-NEXT:    ret
118;
119; RV64-LABEL: test7:
120; RV64:       # %bb.0:
121; RV64-NEXT:    xori a0, a0, 31
122; RV64-NEXT:    slli a0, a0, 40
123; RV64-NEXT:    ret
124  %xor = shl i64 %x, 40
125  %shl = xor i64 %xor, 34084860461056
126  ret i64 %shl
127}
128
129define i64 @test8(i64 %x) nounwind {
130; RV32-LABEL: test8:
131; RV32:       # %bb.0:
132; RV32-NEXT:    slli a0, a0, 1
133; RV32-NEXT:    andi a1, a0, -482
134; RV32-NEXT:    li a0, 0
135; RV32-NEXT:    ret
136;
137; RV64-LABEL: test8:
138; RV64:       # %bb.0:
139; RV64-NEXT:    andi a0, a0, -241
140; RV64-NEXT:    slli a0, a0, 33
141; RV64-NEXT:    ret
142  %xor = shl i64 %x, 33
143  %shl = and i64 %xor, -2070174236672
144  ret i64 %shl
145}
146
147define i64 @test9(i64 %x) nounwind {
148; RV32-LABEL: test9:
149; RV32:       # %bb.0:
150; RV32-NEXT:    slli a0, a0, 1
151; RV32-NEXT:    ori a1, a0, -482
152; RV32-NEXT:    li a0, 0
153; RV32-NEXT:    ret
154;
155; RV64-LABEL: test9:
156; RV64:       # %bb.0:
157; RV64-NEXT:    ori a0, a0, -241
158; RV64-NEXT:    slli a0, a0, 33
159; RV64-NEXT:    ret
160  %xor = shl i64 %x, 33
161  %shl = or i64 %xor, -2070174236672
162  ret i64 %shl
163}
164
165define i64 @test10(i64 %x) nounwind {
166; RV32-LABEL: test10:
167; RV32:       # %bb.0:
168; RV32-NEXT:    slli a0, a0, 1
169; RV32-NEXT:    xori a1, a0, -482
170; RV32-NEXT:    li a0, 0
171; RV32-NEXT:    ret
172;
173; RV64-LABEL: test10:
174; RV64:       # %bb.0:
175; RV64-NEXT:    xori a0, a0, -241
176; RV64-NEXT:    slli a0, a0, 33
177; RV64-NEXT:    ret
178  %xor = shl i64 %x, 33
179  %shl = xor i64 %xor, -2070174236672
180  ret i64 %shl
181}
182
183define signext i32 @test11(i32 signext %x) nounwind {
184; RV32-LABEL: test11:
185; RV32:       # %bb.0:
186; RV32-NEXT:    andi a0, a0, -241
187; RV32-NEXT:    slli a0, a0, 17
188; RV32-NEXT:    ret
189;
190; RV64-LABEL: test11:
191; RV64:       # %bb.0:
192; RV64-NEXT:    andi a0, a0, -241
193; RV64-NEXT:    slliw a0, a0, 17
194; RV64-NEXT:    ret
195  %or = shl i32 %x, 17
196  %shl = and i32 %or, -31588352
197  ret i32 %shl
198}
199
200define signext i32 @test12(i32 signext %x) nounwind {
201; RV32-LABEL: test12:
202; RV32:       # %bb.0:
203; RV32-NEXT:    ori a0, a0, -241
204; RV32-NEXT:    slli a0, a0, 17
205; RV32-NEXT:    ret
206;
207; RV64-LABEL: test12:
208; RV64:       # %bb.0:
209; RV64-NEXT:    ori a0, a0, -241
210; RV64-NEXT:    slli a0, a0, 17
211; RV64-NEXT:    ret
212  %or = shl i32 %x, 17
213  %shl = or i32 %or, -31588352
214  ret i32 %shl
215}
216
217define signext i32 @test13(i32 signext %x) nounwind {
218; RV32-LABEL: test13:
219; RV32:       # %bb.0:
220; RV32-NEXT:    xori a0, a0, -241
221; RV32-NEXT:    slli a0, a0, 17
222; RV32-NEXT:    ret
223;
224; RV64-LABEL: test13:
225; RV64:       # %bb.0:
226; RV64-NEXT:    xori a0, a0, -241
227; RV64-NEXT:    slliw a0, a0, 17
228; RV64-NEXT:    ret
229  %or = shl i32 %x, 17
230  %shl = xor i32 %or, -31588352
231  ret i32 %shl
232}
233
234; Negative test. Can't transform because the constant has a 1 in the bits
235; cleared by the shl.
236define signext i32 @test14(i32 signext %x) nounwind {
237; RV32-LABEL: test14:
238; RV32:       # %bb.0:
239; RV32-NEXT:    slli a0, a0, 10
240; RV32-NEXT:    lui a1, 8
241; RV32-NEXT:    addi a1, a1, -1027
242; RV32-NEXT:    or a0, a0, a1
243; RV32-NEXT:    ret
244;
245; RV64-LABEL: test14:
246; RV64:       # %bb.0:
247; RV64-NEXT:    slliw a0, a0, 10
248; RV64-NEXT:    lui a1, 8
249; RV64-NEXT:    addiw a1, a1, -1027
250; RV64-NEXT:    or a0, a0, a1
251; RV64-NEXT:    ret
252  %or = shl i32 %x, 10
253  %shl = or i32 %or, 31741
254  ret i32 %shl
255}
256
257; Negative test. Can't transform because the constant has a 1 in the bits
258; cleared by the shl.
259define signext i32 @test15(i32 signext %x) nounwind {
260; RV32-LABEL: test15:
261; RV32:       # %bb.0:
262; RV32-NEXT:    slli a0, a0, 10
263; RV32-NEXT:    lui a1, 8
264; RV32-NEXT:    addi a1, a1, -515
265; RV32-NEXT:    xor a0, a0, a1
266; RV32-NEXT:    ret
267;
268; RV64-LABEL: test15:
269; RV64:       # %bb.0:
270; RV64-NEXT:    slliw a0, a0, 10
271; RV64-NEXT:    lui a1, 8
272; RV64-NEXT:    addiw a1, a1, -515
273; RV64-NEXT:    xor a0, a0, a1
274; RV64-NEXT:    ret
275  %xor = shl i32 %x, 10
276  %shl = xor i32 %xor, 32253
277  ret i32 %shl
278}
279