xref: /llvm-project/llvm/test/CodeGen/RISCV/machineoutliner.mir (revision 80df56e03b0455382cec51557bfc9f099d5c0a6f) 
1# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
2# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s
3# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
4# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s
5
6--- |
7  define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
8
9  define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
10
11  define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
12
13  ; Should not outline linkonce_odr functions which could be deduplicated by the
14  ; linker.
15  define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }
16
17  ; Should not outline functions with named linker sections
18  define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }
19
20  ; Cannot outline if the X5 (t0) register is not free
21  define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }
22
23...
24---
25name:            outline_0
26tracksRegLiveness: true
27isOutlined: false
28body:             |
29  bb.0:
30    liveins: $x10, $x11
31    ; RV32I-MO-LABEL: name: outline_0
32    ; RV32I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
33    ;
34    ; RV64I-MO-LABEL: name: outline_0
35    ; RV64I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
36    $x11 = ORI $x11, 1023
37    $x12 = ADDI $x10, 17
38    $x11 = AND $x12, $x11
39    $x10 = SUB $x10, $x11
40    PseudoRET implicit $x10
41
42...
43---
44name:            outline_1
45tracksRegLiveness: true
46isOutlined: false
47body:             |
48  bb.0:
49    liveins: $x10, $x11
50    ; RV32I-MO-LABEL: name: outline_1
51    ; RV32I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
52    ;
53    ; RV64I-MO-LABEL: name: outline_1
54    ; RV64I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
55    $x11 = ORI $x11, 1023
56    $x12 = ADDI $x10, 17
57    $x11 = AND $x12, $x11
58    $x10 = SUB $x10, $x11
59    PseudoRET implicit $x10
60
61...
62---
63name:            outline_2
64tracksRegLiveness: true
65isOutlined: false
66body:             |
67  bb.0:
68    liveins: $x10, $x11
69    ; RV32I-MO-LABEL: name: outline_2
70    ; RV32I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
71    ;
72    ; RV64I-MO-LABEL: name: outline_2
73    ; RV64I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
74    $x11 = ORI $x11, 1023
75    $x12 = ADDI $x10, 17
76    $x11 = AND $x12, $x11
77    $x10 = SUB $x10, $x11
78    PseudoRET implicit $x10
79
80...
81---
82name:            dont_outline_0
83tracksRegLiveness: true
84isOutlined: false
85body:             |
86  bb.0:
87    liveins: $x10, $x11
88    ; RV32I-MO-LABEL: name: dont_outline_0
89    ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
90    ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
91    ;
92    ; RV64I-MO-LABEL: name: dont_outline_0
93    ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
94    ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
95    $x11 = ORI $x11, 1023
96    $x12 = ADDI $x10, 17
97    $x11 = AND $x12, $x11
98    $x10 = SUB $x10, $x11
99    PseudoRET implicit $x10
100
101...
102---
103name:            dont_outline_1
104tracksRegLiveness: true
105isOutlined: false
106body:             |
107  bb.0:
108    liveins: $x10, $x11
109    ; RV32I-MO-LABEL: name: dont_outline_1
110    ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
111    ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
112    ;
113    ; RV64I-MO-LABEL: name: dont_outline_1
114    ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
115    ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
116    $x11 = ORI $x11, 1023
117    $x12 = ADDI $x10, 17
118    $x11 = AND $x12, $x11
119    $x10 = SUB $x10, $x11
120    PseudoRET implicit $x10
121
122...
123---
124name:            dont_outline_2
125tracksRegLiveness: true
126isOutlined: false
127body:             |
128  bb.0:
129    liveins: $x10, $x11, $x5
130    ; RV32I-MO-LABEL: name: dont_outline_2
131    ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
132    ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
133    ;
134    ; RV64I-MO-LABEL: name: dont_outline_2
135    ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
136    ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
137    $x11 = ORI $x11, 1023
138    $x12 = ADDI $x10, 17
139    $x11 = AND $x12, $x11
140    $x10 = SUB $x10, $x11
141    $x10 = ADD $x10, $x5
142    PseudoRET implicit $x10
143
144...
145
146# CHECK-LABEL: name: OUTLINED_FUNCTION_0
147# CHECK: isOutlined: true
148