1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ 3# RUN: | FileCheck -check-prefixes=RV32I-MO %s 4# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ 5# RUN: | FileCheck -check-prefixes=RV64I-MO %s 6 7# Position instructions are illegal to outline. The first instruction won't be outlined 8# because position instructions break the sequence. 9 10--- | 11 define void @func1(i32 %a, i32 %b) { ret void } 12 13 define void @func2(i32 %a, i32 %b) { ret void } 14 15 define void @func3(i32 %a, i32 %b) { ret void } 16... 17--- 18name: func1 19tracksRegLiveness: true 20body: | 21 bb.0: 22 liveins: $x10, $x11 23 ; RV32I-MO-LABEL: name: func1 24 ; RV32I-MO: liveins: $x10, $x11 25 ; RV32I-MO-NEXT: {{ $}} 26 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 27 ; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0> 28 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 29 ; 30 ; RV64I-MO-LABEL: name: func1 31 ; RV64I-MO: liveins: $x10, $x11 32 ; RV64I-MO-NEXT: {{ $}} 33 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 34 ; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0> 35 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 36 $x10 = ORI $x10, 1023 37 EH_LABEL <mcsymbol .Ltmp0> 38 $x11 = ORI $x11, 1023 39 $x12 = ADDI $x10, 17 40 $x11 = AND $x12, $x11 41 $x10 = SUB $x10, $x11 42 PseudoRET 43... 44--- 45name: func2 46tracksRegLiveness: true 47body: | 48 bb.0: 49 liveins: $x10, $x11 50 ; RV32I-MO-LABEL: name: func2 51 ; RV32I-MO: liveins: $x10, $x11 52 ; RV32I-MO-NEXT: {{ $}} 53 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 54 ; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1> 55 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 56 ; 57 ; RV64I-MO-LABEL: name: func2 58 ; RV64I-MO: liveins: $x10, $x11 59 ; RV64I-MO-NEXT: {{ $}} 60 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 61 ; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1> 62 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 63 $x10 = ORI $x10, 1023 64 GC_LABEL <mcsymbol .Ltmp1> 65 $x11 = ORI $x11, 1023 66 $x12 = ADDI $x10, 17 67 $x11 = AND $x12, $x11 68 $x10 = SUB $x10, $x11 69 PseudoRET 70... 71--- 72name: func3 73tracksRegLiveness: true 74body: | 75 bb.0: 76 liveins: $x10, $x11 77 ; RV32I-MO-LABEL: name: func3 78 ; RV32I-MO: liveins: $x10, $x11 79 ; RV32I-MO-NEXT: {{ $}} 80 ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 81 ; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2> 82 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 83 ; 84 ; RV64I-MO-LABEL: name: func3 85 ; RV64I-MO: liveins: $x10, $x11 86 ; RV64I-MO-NEXT: {{ $}} 87 ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 88 ; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2> 89 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 90 $x10 = ORI $x10, 1023 91 ANNOTATION_LABEL <mcsymbol .Ltmp2> 92 $x11 = ORI $x11, 1023 93 $x12 = ADDI $x10, 17 94 $x11 = AND $x12, $x11 95 $x10 = SUB $x10, $x11 96 PseudoRET 97