1# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ 2# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s 3# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ 4# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s 5 6# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there 7# is no need to unwind. CFIs will be stripped when we build outlined functions. 8 9--- | 10 define void @func1(i32 %a, i32 %b) nounwind { ret void } 11 12 define void @func2(i32 %a, i32 %b) nounwind { ret void } 13 14 define void @func3(i32 %a, i32 %b) nounwind { ret void } 15... 16--- 17name: func1 18tracksRegLiveness: true 19body: | 20 bb.0: 21 liveins: $x10, $x11 22 ; RV32I-MO-LABEL: name: func1 23 ; RV32I-MO: liveins: $x10, $x11 24 ; RV32I-MO-NEXT: {{ $}} 25 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 26 ; RV64I-MO-LABEL: name: func1 27 ; RV64I-MO: liveins: $x10, $x11 28 ; RV64I-MO-NEXT: {{ $}} 29 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 30 $x10 = ORI $x10, 1023 31 CFI_INSTRUCTION offset $x1, 0 32 $x11 = ORI $x11, 1023 33 CFI_INSTRUCTION offset $x1, -4 34 $x12 = ADDI $x10, 17 35 CFI_INSTRUCTION offset $x1, -8 36 $x11 = AND $x12, $x11 37 CFI_INSTRUCTION offset $x1, -12 38 $x10 = SUB $x10, $x11 39 PseudoRET 40... 41--- 42name: func2 43tracksRegLiveness: true 44body: | 45 bb.0: 46 liveins: $x10, $x11 47 ; RV32I-MO-LABEL: name: func2 48 ; RV32I-MO: liveins: $x10, $x11 49 ; RV32I-MO-NEXT: {{ $}} 50 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 51 ; RV64I-MO-LABEL: name: func2 52 ; RV64I-MO: liveins: $x10, $x11 53 ; RV64I-MO-NEXT: {{ $}} 54 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 55 $x10 = ORI $x10, 1023 56 CFI_INSTRUCTION offset $x1, 0 57 $x11 = ORI $x11, 1023 58 CFI_INSTRUCTION offset $x1, -8 59 $x12 = ADDI $x10, 17 60 CFI_INSTRUCTION offset $x1, -4 61 $x11 = AND $x12, $x11 62 CFI_INSTRUCTION offset $x1, -12 63 $x10 = SUB $x10, $x11 64 PseudoRET 65... 66--- 67name: func3 68tracksRegLiveness: true 69body: | 70 bb.0: 71 liveins: $x10, $x11 72 ; RV32I-MO-LABEL: name: func3 73 ; RV32I-MO: liveins: $x10, $x11 74 ; RV32I-MO-NEXT: {{ $}} 75 ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 76 ; RV64I-MO-LABEL: name: func3 77 ; RV64I-MO: liveins: $x10, $x11 78 ; RV64I-MO-NEXT: {{ $}} 79 ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 80 $x10 = ORI $x10, 1023 81 CFI_INSTRUCTION offset $x1, -12 82 $x11 = ORI $x11, 1023 83 CFI_INSTRUCTION offset $x1, -8 84 $x12 = ADDI $x10, 17 85 CFI_INSTRUCTION offset $x1, -4 86 $x11 = AND $x12, $x11 87 CFI_INSTRUCTION offset $x1, 0 88 $x10 = SUB $x10, $x11 89 PseudoRET 90 91 92# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0 93# OUTLINED: liveins: $x11, $x10 94# OUTLINED-NEXT: {{ $}} 95# OUTLINED-NEXT: $x10 = ORI $x10, 1023 96# OUTLINED-NEXT: $x11 = ORI $x11, 1023 97# OUTLINED-NEXT: $x12 = ADDI $x10, 17 98# OUTLINED-NEXT: $x11 = AND $x12, $x11 99# OUTLINED-NEXT: $x10 = SUB $x10, $x11 100# OUTLINED-NEXT: PseudoRET 101