1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32 %s 4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64 %s 6 7define void @test1(ptr %a, ptr %b) nounwind { 8; RV32-LABEL: test1: 9; RV32: # %bb.0: # %entry 10; RV32-NEXT: lw a1, 0(a1) 11; RV32-NEXT: lui a2, 524288 12; RV32-NEXT: xor a1, a1, a2 13; RV32-NEXT: sw a1, 0(a0) 14; RV32-NEXT: ret 15; 16; RV64-LABEL: test1: 17; RV64: # %bb.0: # %entry 18; RV64-NEXT: lw a1, 0(a1) 19; RV64-NEXT: lui a2, 524288 20; RV64-NEXT: xor a1, a1, a2 21; RV64-NEXT: sw a1, 0(a0) 22; RV64-NEXT: ret 23entry: 24 %0 = load float, ptr %b 25 %neg = fneg float %0 26 store float %neg, ptr %a 27 ret void 28} 29 30define void @test2(ptr %a, ptr %b) nounwind { 31; RV32-LABEL: test2: 32; RV32: # %bb.0: # %entry 33; RV32-NEXT: lw a2, 4(a1) 34; RV32-NEXT: lw a1, 0(a1) 35; RV32-NEXT: lui a3, 524288 36; RV32-NEXT: xor a2, a2, a3 37; RV32-NEXT: sw a1, 0(a0) 38; RV32-NEXT: sw a2, 4(a0) 39; RV32-NEXT: ret 40; 41; RV64-LABEL: test2: 42; RV64: # %bb.0: # %entry 43; RV64-NEXT: ld a1, 0(a1) 44; RV64-NEXT: li a2, -1 45; RV64-NEXT: slli a2, a2, 63 46; RV64-NEXT: xor a1, a1, a2 47; RV64-NEXT: sd a1, 0(a0) 48; RV64-NEXT: ret 49entry: 50 %0 = load double, ptr %b 51 %neg = fneg double %0 52 store double %neg, ptr %a 53 ret void 54} 55 56define void @test3(ptr %a, ptr %b) nounwind { 57; RV32-LABEL: test3: 58; RV32: # %bb.0: # %entry 59; RV32-NEXT: lw a2, 12(a1) 60; RV32-NEXT: lw a3, 0(a1) 61; RV32-NEXT: lw a4, 4(a1) 62; RV32-NEXT: lw a1, 8(a1) 63; RV32-NEXT: lui a5, 524288 64; RV32-NEXT: xor a2, a2, a5 65; RV32-NEXT: sw a3, 0(a0) 66; RV32-NEXT: sw a4, 4(a0) 67; RV32-NEXT: sw a1, 8(a0) 68; RV32-NEXT: sw a2, 12(a0) 69; RV32-NEXT: ret 70; 71; RV64-LABEL: test3: 72; RV64: # %bb.0: # %entry 73; RV64-NEXT: ld a2, 8(a1) 74; RV64-NEXT: ld a1, 0(a1) 75; RV64-NEXT: li a3, -1 76; RV64-NEXT: slli a3, a3, 63 77; RV64-NEXT: xor a2, a2, a3 78; RV64-NEXT: sd a1, 0(a0) 79; RV64-NEXT: sd a2, 8(a0) 80; RV64-NEXT: ret 81entry: 82 %0 = load fp128, ptr %b 83 %neg = fneg fp128 %0 84 store fp128 %neg, ptr %a 85 ret void 86} 87