xref: /llvm-project/llvm/test/CodeGen/RISCV/jumptable.ll (revision 5973272af796b33b75467ba8fba8b0a98b42757a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL
4; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM
6; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-PIC
8; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
9; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL
10; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
11; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM
12; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
13; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-PIC
14; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
15; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES
16; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
17; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES
18; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
19; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-PIC-7-ENTRIES
20; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
21; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL-7-ENTRIES
22; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
23; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM-7-ENTRIES
24; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
25; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-PIC-7-ENTRIES
26
27define void @below_threshold(i32 signext %in, ptr %out) nounwind {
28; CHECK-LABEL: below_threshold:
29; CHECK:       # %bb.0: # %entry
30; CHECK-NEXT:    li a2, 2
31; CHECK-NEXT:    blt a2, a0, .LBB0_4
32; CHECK-NEXT:  # %bb.1: # %entry
33; CHECK-NEXT:    li a2, 1
34; CHECK-NEXT:    beq a0, a2, .LBB0_7
35; CHECK-NEXT:  # %bb.2: # %entry
36; CHECK-NEXT:    li a2, 2
37; CHECK-NEXT:    bne a0, a2, .LBB0_10
38; CHECK-NEXT:  # %bb.3: # %bb2
39; CHECK-NEXT:    li a0, 3
40; CHECK-NEXT:    j .LBB0_9
41; CHECK-NEXT:  .LBB0_4: # %entry
42; CHECK-NEXT:    li a2, 3
43; CHECK-NEXT:    beq a0, a2, .LBB0_8
44; CHECK-NEXT:  # %bb.5: # %entry
45; CHECK-NEXT:    li a2, 4
46; CHECK-NEXT:    bne a0, a2, .LBB0_10
47; CHECK-NEXT:  # %bb.6: # %bb4
48; CHECK-NEXT:    li a0, 1
49; CHECK-NEXT:    j .LBB0_9
50; CHECK-NEXT:  .LBB0_7: # %bb1
51; CHECK-NEXT:    li a0, 4
52; CHECK-NEXT:    j .LBB0_9
53; CHECK-NEXT:  .LBB0_8: # %bb3
54; CHECK-NEXT:    li a0, 2
55; CHECK-NEXT:  .LBB0_9: # %exit
56; CHECK-NEXT:    sw a0, 0(a1)
57; CHECK-NEXT:  .LBB0_10: # %exit
58; CHECK-NEXT:    ret
59entry:
60  switch i32 %in, label %exit [
61    i32 1, label %bb1
62    i32 2, label %bb2
63    i32 3, label %bb3
64    i32 4, label %bb4
65  ]
66bb1:
67  store i32 4, ptr %out
68  br label %exit
69bb2:
70  store i32 3, ptr %out
71  br label %exit
72bb3:
73  store i32 2, ptr %out
74  br label %exit
75bb4:
76  store i32 1, ptr %out
77  br label %exit
78exit:
79  ret void
80}
81
82define void @above_threshold(i32 signext %in, ptr %out) nounwind {
83; RV32I-SMALL-LABEL: above_threshold:
84; RV32I-SMALL:       # %bb.0: # %entry
85; RV32I-SMALL-NEXT:    addi a0, a0, -1
86; RV32I-SMALL-NEXT:    li a2, 5
87; RV32I-SMALL-NEXT:    bltu a2, a0, .LBB1_9
88; RV32I-SMALL-NEXT:  # %bb.1: # %entry
89; RV32I-SMALL-NEXT:    slli a0, a0, 2
90; RV32I-SMALL-NEXT:    lui a2, %hi(.LJTI1_0)
91; RV32I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI1_0)
92; RV32I-SMALL-NEXT:    add a0, a0, a2
93; RV32I-SMALL-NEXT:    lw a0, 0(a0)
94; RV32I-SMALL-NEXT:    jr a0
95; RV32I-SMALL-NEXT:  .LBB1_2: # %bb1
96; RV32I-SMALL-NEXT:    li a0, 4
97; RV32I-SMALL-NEXT:    j .LBB1_8
98; RV32I-SMALL-NEXT:  .LBB1_3: # %bb5
99; RV32I-SMALL-NEXT:    li a0, 100
100; RV32I-SMALL-NEXT:    j .LBB1_8
101; RV32I-SMALL-NEXT:  .LBB1_4: # %bb3
102; RV32I-SMALL-NEXT:    li a0, 2
103; RV32I-SMALL-NEXT:    j .LBB1_8
104; RV32I-SMALL-NEXT:  .LBB1_5: # %bb4
105; RV32I-SMALL-NEXT:    li a0, 1
106; RV32I-SMALL-NEXT:    j .LBB1_8
107; RV32I-SMALL-NEXT:  .LBB1_6: # %bb2
108; RV32I-SMALL-NEXT:    li a0, 3
109; RV32I-SMALL-NEXT:    j .LBB1_8
110; RV32I-SMALL-NEXT:  .LBB1_7: # %bb6
111; RV32I-SMALL-NEXT:    li a0, 200
112; RV32I-SMALL-NEXT:  .LBB1_8: # %exit
113; RV32I-SMALL-NEXT:    sw a0, 0(a1)
114; RV32I-SMALL-NEXT:  .LBB1_9: # %exit
115; RV32I-SMALL-NEXT:    ret
116;
117; RV32I-MEDIUM-LABEL: above_threshold:
118; RV32I-MEDIUM:       # %bb.0: # %entry
119; RV32I-MEDIUM-NEXT:    addi a0, a0, -1
120; RV32I-MEDIUM-NEXT:    li a2, 5
121; RV32I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
122; RV32I-MEDIUM-NEXT:  # %bb.1: # %entry
123; RV32I-MEDIUM-NEXT:    slli a0, a0, 2
124; RV32I-MEDIUM-NEXT:  .Lpcrel_hi0:
125; RV32I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
126; RV32I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
127; RV32I-MEDIUM-NEXT:    add a0, a0, a2
128; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
129; RV32I-MEDIUM-NEXT:    jr a0
130; RV32I-MEDIUM-NEXT:  .LBB1_2: # %bb1
131; RV32I-MEDIUM-NEXT:    li a0, 4
132; RV32I-MEDIUM-NEXT:    j .LBB1_8
133; RV32I-MEDIUM-NEXT:  .LBB1_3: # %bb5
134; RV32I-MEDIUM-NEXT:    li a0, 100
135; RV32I-MEDIUM-NEXT:    j .LBB1_8
136; RV32I-MEDIUM-NEXT:  .LBB1_4: # %bb3
137; RV32I-MEDIUM-NEXT:    li a0, 2
138; RV32I-MEDIUM-NEXT:    j .LBB1_8
139; RV32I-MEDIUM-NEXT:  .LBB1_5: # %bb4
140; RV32I-MEDIUM-NEXT:    li a0, 1
141; RV32I-MEDIUM-NEXT:    j .LBB1_8
142; RV32I-MEDIUM-NEXT:  .LBB1_6: # %bb2
143; RV32I-MEDIUM-NEXT:    li a0, 3
144; RV32I-MEDIUM-NEXT:    j .LBB1_8
145; RV32I-MEDIUM-NEXT:  .LBB1_7: # %bb6
146; RV32I-MEDIUM-NEXT:    li a0, 200
147; RV32I-MEDIUM-NEXT:  .LBB1_8: # %exit
148; RV32I-MEDIUM-NEXT:    sw a0, 0(a1)
149; RV32I-MEDIUM-NEXT:  .LBB1_9: # %exit
150; RV32I-MEDIUM-NEXT:    ret
151;
152; RV32I-PIC-LABEL: above_threshold:
153; RV32I-PIC:       # %bb.0: # %entry
154; RV32I-PIC-NEXT:    addi a0, a0, -1
155; RV32I-PIC-NEXT:    li a2, 5
156; RV32I-PIC-NEXT:    bltu a2, a0, .LBB1_9
157; RV32I-PIC-NEXT:  # %bb.1: # %entry
158; RV32I-PIC-NEXT:    slli a0, a0, 2
159; RV32I-PIC-NEXT:  .Lpcrel_hi0:
160; RV32I-PIC-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
161; RV32I-PIC-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
162; RV32I-PIC-NEXT:    add a0, a0, a2
163; RV32I-PIC-NEXT:    lw a0, 0(a0)
164; RV32I-PIC-NEXT:    add a0, a0, a2
165; RV32I-PIC-NEXT:    jr a0
166; RV32I-PIC-NEXT:  .LBB1_2: # %bb1
167; RV32I-PIC-NEXT:    li a0, 4
168; RV32I-PIC-NEXT:    j .LBB1_8
169; RV32I-PIC-NEXT:  .LBB1_3: # %bb5
170; RV32I-PIC-NEXT:    li a0, 100
171; RV32I-PIC-NEXT:    j .LBB1_8
172; RV32I-PIC-NEXT:  .LBB1_4: # %bb3
173; RV32I-PIC-NEXT:    li a0, 2
174; RV32I-PIC-NEXT:    j .LBB1_8
175; RV32I-PIC-NEXT:  .LBB1_5: # %bb4
176; RV32I-PIC-NEXT:    li a0, 1
177; RV32I-PIC-NEXT:    j .LBB1_8
178; RV32I-PIC-NEXT:  .LBB1_6: # %bb2
179; RV32I-PIC-NEXT:    li a0, 3
180; RV32I-PIC-NEXT:    j .LBB1_8
181; RV32I-PIC-NEXT:  .LBB1_7: # %bb6
182; RV32I-PIC-NEXT:    li a0, 200
183; RV32I-PIC-NEXT:  .LBB1_8: # %exit
184; RV32I-PIC-NEXT:    sw a0, 0(a1)
185; RV32I-PIC-NEXT:  .LBB1_9: # %exit
186; RV32I-PIC-NEXT:    ret
187;
188; RV64I-SMALL-LABEL: above_threshold:
189; RV64I-SMALL:       # %bb.0: # %entry
190; RV64I-SMALL-NEXT:    addi a0, a0, -1
191; RV64I-SMALL-NEXT:    li a2, 5
192; RV64I-SMALL-NEXT:    bltu a2, a0, .LBB1_9
193; RV64I-SMALL-NEXT:  # %bb.1: # %entry
194; RV64I-SMALL-NEXT:    slli a0, a0, 2
195; RV64I-SMALL-NEXT:    lui a2, %hi(.LJTI1_0)
196; RV64I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI1_0)
197; RV64I-SMALL-NEXT:    add a0, a0, a2
198; RV64I-SMALL-NEXT:    lw a0, 0(a0)
199; RV64I-SMALL-NEXT:    jr a0
200; RV64I-SMALL-NEXT:  .LBB1_2: # %bb1
201; RV64I-SMALL-NEXT:    li a0, 4
202; RV64I-SMALL-NEXT:    j .LBB1_8
203; RV64I-SMALL-NEXT:  .LBB1_3: # %bb5
204; RV64I-SMALL-NEXT:    li a0, 100
205; RV64I-SMALL-NEXT:    j .LBB1_8
206; RV64I-SMALL-NEXT:  .LBB1_4: # %bb3
207; RV64I-SMALL-NEXT:    li a0, 2
208; RV64I-SMALL-NEXT:    j .LBB1_8
209; RV64I-SMALL-NEXT:  .LBB1_5: # %bb4
210; RV64I-SMALL-NEXT:    li a0, 1
211; RV64I-SMALL-NEXT:    j .LBB1_8
212; RV64I-SMALL-NEXT:  .LBB1_6: # %bb2
213; RV64I-SMALL-NEXT:    li a0, 3
214; RV64I-SMALL-NEXT:    j .LBB1_8
215; RV64I-SMALL-NEXT:  .LBB1_7: # %bb6
216; RV64I-SMALL-NEXT:    li a0, 200
217; RV64I-SMALL-NEXT:  .LBB1_8: # %exit
218; RV64I-SMALL-NEXT:    sw a0, 0(a1)
219; RV64I-SMALL-NEXT:  .LBB1_9: # %exit
220; RV64I-SMALL-NEXT:    ret
221;
222; RV64I-MEDIUM-LABEL: above_threshold:
223; RV64I-MEDIUM:       # %bb.0: # %entry
224; RV64I-MEDIUM-NEXT:    addi a0, a0, -1
225; RV64I-MEDIUM-NEXT:    li a2, 5
226; RV64I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
227; RV64I-MEDIUM-NEXT:  # %bb.1: # %entry
228; RV64I-MEDIUM-NEXT:    slli a0, a0, 3
229; RV64I-MEDIUM-NEXT:  .Lpcrel_hi0:
230; RV64I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
231; RV64I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
232; RV64I-MEDIUM-NEXT:    add a0, a0, a2
233; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
234; RV64I-MEDIUM-NEXT:    jr a0
235; RV64I-MEDIUM-NEXT:  .LBB1_2: # %bb1
236; RV64I-MEDIUM-NEXT:    li a0, 4
237; RV64I-MEDIUM-NEXT:    j .LBB1_8
238; RV64I-MEDIUM-NEXT:  .LBB1_3: # %bb5
239; RV64I-MEDIUM-NEXT:    li a0, 100
240; RV64I-MEDIUM-NEXT:    j .LBB1_8
241; RV64I-MEDIUM-NEXT:  .LBB1_4: # %bb3
242; RV64I-MEDIUM-NEXT:    li a0, 2
243; RV64I-MEDIUM-NEXT:    j .LBB1_8
244; RV64I-MEDIUM-NEXT:  .LBB1_5: # %bb4
245; RV64I-MEDIUM-NEXT:    li a0, 1
246; RV64I-MEDIUM-NEXT:    j .LBB1_8
247; RV64I-MEDIUM-NEXT:  .LBB1_6: # %bb2
248; RV64I-MEDIUM-NEXT:    li a0, 3
249; RV64I-MEDIUM-NEXT:    j .LBB1_8
250; RV64I-MEDIUM-NEXT:  .LBB1_7: # %bb6
251; RV64I-MEDIUM-NEXT:    li a0, 200
252; RV64I-MEDIUM-NEXT:  .LBB1_8: # %exit
253; RV64I-MEDIUM-NEXT:    sw a0, 0(a1)
254; RV64I-MEDIUM-NEXT:  .LBB1_9: # %exit
255; RV64I-MEDIUM-NEXT:    ret
256;
257; RV64I-PIC-LABEL: above_threshold:
258; RV64I-PIC:       # %bb.0: # %entry
259; RV64I-PIC-NEXT:    addi a0, a0, -1
260; RV64I-PIC-NEXT:    li a2, 5
261; RV64I-PIC-NEXT:    bltu a2, a0, .LBB1_9
262; RV64I-PIC-NEXT:  # %bb.1: # %entry
263; RV64I-PIC-NEXT:    slli a0, a0, 2
264; RV64I-PIC-NEXT:  .Lpcrel_hi0:
265; RV64I-PIC-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
266; RV64I-PIC-NEXT:    addi a2, a2, %pcrel_lo(.Lpcrel_hi0)
267; RV64I-PIC-NEXT:    add a0, a0, a2
268; RV64I-PIC-NEXT:    lw a0, 0(a0)
269; RV64I-PIC-NEXT:    add a0, a0, a2
270; RV64I-PIC-NEXT:    jr a0
271; RV64I-PIC-NEXT:  .LBB1_2: # %bb1
272; RV64I-PIC-NEXT:    li a0, 4
273; RV64I-PIC-NEXT:    j .LBB1_8
274; RV64I-PIC-NEXT:  .LBB1_3: # %bb5
275; RV64I-PIC-NEXT:    li a0, 100
276; RV64I-PIC-NEXT:    j .LBB1_8
277; RV64I-PIC-NEXT:  .LBB1_4: # %bb3
278; RV64I-PIC-NEXT:    li a0, 2
279; RV64I-PIC-NEXT:    j .LBB1_8
280; RV64I-PIC-NEXT:  .LBB1_5: # %bb4
281; RV64I-PIC-NEXT:    li a0, 1
282; RV64I-PIC-NEXT:    j .LBB1_8
283; RV64I-PIC-NEXT:  .LBB1_6: # %bb2
284; RV64I-PIC-NEXT:    li a0, 3
285; RV64I-PIC-NEXT:    j .LBB1_8
286; RV64I-PIC-NEXT:  .LBB1_7: # %bb6
287; RV64I-PIC-NEXT:    li a0, 200
288; RV64I-PIC-NEXT:  .LBB1_8: # %exit
289; RV64I-PIC-NEXT:    sw a0, 0(a1)
290; RV64I-PIC-NEXT:  .LBB1_9: # %exit
291; RV64I-PIC-NEXT:    ret
292;
293; RV32I-SMALL-7-ENTRIES-LABEL: above_threshold:
294; RV32I-SMALL-7-ENTRIES:       # %bb.0: # %entry
295; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 3
296; RV32I-SMALL-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
297; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.1: # %entry
298; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 1
299; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
300; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.2: # %entry
301; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 2
302; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
303; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.3: # %entry
304; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 3
305; RV32I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
306; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.4: # %bb3
307; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 2
308; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
309; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_5: # %entry
310; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 4
311; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
312; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.6: # %entry
313; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 5
314; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
315; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.7: # %entry
316; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 6
317; RV32I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
318; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.8: # %bb6
319; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 200
320; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
321; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
322; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 4
323; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
324; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
325; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 1
326; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
327; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
328; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 3
329; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
330; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
331; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 100
332; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_13: # %exit
333; RV32I-SMALL-7-ENTRIES-NEXT:    sw a0, 0(a1)
334; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
335; RV32I-SMALL-7-ENTRIES-NEXT:    ret
336;
337; RV32I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
338; RV32I-MEDIUM-7-ENTRIES:       # %bb.0: # %entry
339; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
340; RV32I-MEDIUM-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
341; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.1: # %entry
342; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 1
343; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
344; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.2: # %entry
345; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 2
346; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
347; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.3: # %entry
348; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
349; RV32I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
350; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.4: # %bb3
351; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 2
352; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
353; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_5: # %entry
354; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 4
355; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
356; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.6: # %entry
357; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 5
358; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
359; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.7: # %entry
360; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 6
361; RV32I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
362; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.8: # %bb6
363; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 200
364; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
365; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
366; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 4
367; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
368; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
369; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 1
370; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
371; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
372; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 3
373; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
374; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
375; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 100
376; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_13: # %exit
377; RV32I-MEDIUM-7-ENTRIES-NEXT:    sw a0, 0(a1)
378; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_14: # %exit
379; RV32I-MEDIUM-7-ENTRIES-NEXT:    ret
380;
381; RV32I-PIC-7-ENTRIES-LABEL: above_threshold:
382; RV32I-PIC-7-ENTRIES:       # %bb.0: # %entry
383; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 3
384; RV32I-PIC-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
385; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.1: # %entry
386; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 1
387; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
388; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.2: # %entry
389; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 2
390; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
391; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.3: # %entry
392; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 3
393; RV32I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
394; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.4: # %bb3
395; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 2
396; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
397; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_5: # %entry
398; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 4
399; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
400; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.6: # %entry
401; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 5
402; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
403; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.7: # %entry
404; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 6
405; RV32I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
406; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.8: # %bb6
407; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 200
408; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
409; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
410; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 4
411; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
412; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
413; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 1
414; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
415; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
416; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 3
417; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
418; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
419; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 100
420; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_13: # %exit
421; RV32I-PIC-7-ENTRIES-NEXT:    sw a0, 0(a1)
422; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_14: # %exit
423; RV32I-PIC-7-ENTRIES-NEXT:    ret
424;
425; RV64I-SMALL-7-ENTRIES-LABEL: above_threshold:
426; RV64I-SMALL-7-ENTRIES:       # %bb.0: # %entry
427; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 3
428; RV64I-SMALL-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
429; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.1: # %entry
430; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 1
431; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
432; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.2: # %entry
433; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 2
434; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
435; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.3: # %entry
436; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 3
437; RV64I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
438; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.4: # %bb3
439; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 2
440; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
441; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_5: # %entry
442; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 4
443; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
444; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.6: # %entry
445; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 5
446; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
447; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.7: # %entry
448; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 6
449; RV64I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
450; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.8: # %bb6
451; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 200
452; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
453; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
454; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 4
455; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
456; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
457; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 1
458; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
459; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
460; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 3
461; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
462; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
463; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 100
464; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_13: # %exit
465; RV64I-SMALL-7-ENTRIES-NEXT:    sw a0, 0(a1)
466; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
467; RV64I-SMALL-7-ENTRIES-NEXT:    ret
468;
469; RV64I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
470; RV64I-MEDIUM-7-ENTRIES:       # %bb.0: # %entry
471; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
472; RV64I-MEDIUM-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
473; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.1: # %entry
474; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 1
475; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
476; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.2: # %entry
477; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 2
478; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
479; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.3: # %entry
480; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
481; RV64I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
482; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.4: # %bb3
483; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 2
484; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
485; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_5: # %entry
486; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 4
487; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
488; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.6: # %entry
489; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 5
490; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
491; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.7: # %entry
492; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 6
493; RV64I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
494; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.8: # %bb6
495; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 200
496; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
497; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
498; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 4
499; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
500; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
501; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 1
502; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
503; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
504; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 3
505; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
506; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
507; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 100
508; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_13: # %exit
509; RV64I-MEDIUM-7-ENTRIES-NEXT:    sw a0, 0(a1)
510; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_14: # %exit
511; RV64I-MEDIUM-7-ENTRIES-NEXT:    ret
512;
513; RV64I-PIC-7-ENTRIES-LABEL: above_threshold:
514; RV64I-PIC-7-ENTRIES:       # %bb.0: # %entry
515; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 3
516; RV64I-PIC-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
517; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.1: # %entry
518; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 1
519; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
520; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.2: # %entry
521; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 2
522; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
523; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.3: # %entry
524; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 3
525; RV64I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
526; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.4: # %bb3
527; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 2
528; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
529; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_5: # %entry
530; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 4
531; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
532; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.6: # %entry
533; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 5
534; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
535; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.7: # %entry
536; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 6
537; RV64I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
538; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.8: # %bb6
539; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 200
540; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
541; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
542; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 4
543; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
544; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
545; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 1
546; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
547; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
548; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 3
549; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
550; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
551; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 100
552; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_13: # %exit
553; RV64I-PIC-7-ENTRIES-NEXT:    sw a0, 0(a1)
554; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_14: # %exit
555; RV64I-PIC-7-ENTRIES-NEXT:    ret
556entry:
557  switch i32 %in, label %exit [
558    i32 1, label %bb1
559    i32 2, label %bb2
560    i32 3, label %bb3
561    i32 4, label %bb4
562    i32 5, label %bb5
563    i32 6, label %bb6
564  ]
565bb1:
566  store i32 4, ptr %out
567  br label %exit
568bb2:
569  store i32 3, ptr %out
570  br label %exit
571bb3:
572  store i32 2, ptr %out
573  br label %exit
574bb4:
575  store i32 1, ptr %out
576  br label %exit
577bb5:
578  store i32 100, ptr %out
579  br label %exit
580bb6:
581  store i32 200, ptr %out
582  br label %exit
583exit:
584  ret void
585}
586