xref: /llvm-project/llvm/test/CodeGen/RISCV/double-maximum-minimum.ll (revision 048458f94c60fc9c200c9dcbcccd4a54ed84b8f9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
3; RUN:   -verify-machineinstrs -target-abi=ilp32d \
4; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
6; RUN:   -verify-machineinstrs -target-abi=lp64d \
7; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
9; RUN:   -verify-machineinstrs -target-abi=ilp32 \
10; RUN:   | FileCheck -check-prefix=RV32IZFINXZDINX %s
11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
12; RUN:   -verify-machineinstrs -target-abi=lp64 \
13; RUN:   | FileCheck -check-prefix=RV64IZFINXZDINX %s
14
15declare double @llvm.minimum.f64(double, double)
16
17define double @fminimum_f64(double %a, double %b) nounwind {
18; CHECKIFD-LABEL: fminimum_f64:
19; CHECKIFD:       # %bb.0:
20; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
21; CHECKIFD-NEXT:    fmv.d fa5, fa1
22; CHECKIFD-NEXT:    beqz a0, .LBB0_3
23; CHECKIFD-NEXT:  # %bb.1:
24; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
25; CHECKIFD-NEXT:    beqz a0, .LBB0_4
26; CHECKIFD-NEXT:  .LBB0_2:
27; CHECKIFD-NEXT:    fmin.d fa0, fa0, fa5
28; CHECKIFD-NEXT:    ret
29; CHECKIFD-NEXT:  .LBB0_3:
30; CHECKIFD-NEXT:    fmv.d fa5, fa0
31; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
32; CHECKIFD-NEXT:    bnez a0, .LBB0_2
33; CHECKIFD-NEXT:  .LBB0_4:
34; CHECKIFD-NEXT:    fmin.d fa0, fa1, fa5
35; CHECKIFD-NEXT:    ret
36;
37; RV32IZFINXZDINX-LABEL: fminimum_f64:
38; RV32IZFINXZDINX:       # %bb.0:
39; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
40; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
41; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
42; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
43; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
44; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
45; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
46; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
47; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
48; RV32IZFINXZDINX-NEXT:    feq.d a6, a0, a0
49; RV32IZFINXZDINX-NEXT:    mv a4, a2
50; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB0_2
51; RV32IZFINXZDINX-NEXT:  # %bb.1:
52; RV32IZFINXZDINX-NEXT:    mv a4, a0
53; RV32IZFINXZDINX-NEXT:  .LBB0_2:
54; RV32IZFINXZDINX-NEXT:    feq.d a6, a2, a2
55; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB0_4
56; RV32IZFINXZDINX-NEXT:  # %bb.3:
57; RV32IZFINXZDINX-NEXT:    mv a0, a2
58; RV32IZFINXZDINX-NEXT:  .LBB0_4:
59; RV32IZFINXZDINX-NEXT:    fmin.d a0, a0, a4
60; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
61; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
62; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
63; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
64; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
65; RV32IZFINXZDINX-NEXT:    ret
66;
67; RV64IZFINXZDINX-LABEL: fminimum_f64:
68; RV64IZFINXZDINX:       # %bb.0:
69; RV64IZFINXZDINX-NEXT:    feq.d a3, a0, a0
70; RV64IZFINXZDINX-NEXT:    mv a2, a1
71; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB0_3
72; RV64IZFINXZDINX-NEXT:  # %bb.1:
73; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
74; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB0_4
75; RV64IZFINXZDINX-NEXT:  .LBB0_2:
76; RV64IZFINXZDINX-NEXT:    fmin.d a0, a0, a2
77; RV64IZFINXZDINX-NEXT:    ret
78; RV64IZFINXZDINX-NEXT:  .LBB0_3:
79; RV64IZFINXZDINX-NEXT:    mv a2, a0
80; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
81; RV64IZFINXZDINX-NEXT:    bnez a3, .LBB0_2
82; RV64IZFINXZDINX-NEXT:  .LBB0_4:
83; RV64IZFINXZDINX-NEXT:    fmin.d a0, a1, a2
84; RV64IZFINXZDINX-NEXT:    ret
85  %1 = call double @llvm.minimum.f64(double %a, double %b)
86  ret double %1
87}
88
89declare double @llvm.maximum.f64(double, double)
90
91define double @fmaximum_f64(double %a, double %b) nounwind {
92; CHECKIFD-LABEL: fmaximum_f64:
93; CHECKIFD:       # %bb.0:
94; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
95; CHECKIFD-NEXT:    fmv.d fa5, fa1
96; CHECKIFD-NEXT:    beqz a0, .LBB1_3
97; CHECKIFD-NEXT:  # %bb.1:
98; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
99; CHECKIFD-NEXT:    beqz a0, .LBB1_4
100; CHECKIFD-NEXT:  .LBB1_2:
101; CHECKIFD-NEXT:    fmax.d fa0, fa0, fa5
102; CHECKIFD-NEXT:    ret
103; CHECKIFD-NEXT:  .LBB1_3:
104; CHECKIFD-NEXT:    fmv.d fa5, fa0
105; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
106; CHECKIFD-NEXT:    bnez a0, .LBB1_2
107; CHECKIFD-NEXT:  .LBB1_4:
108; CHECKIFD-NEXT:    fmax.d fa0, fa1, fa5
109; CHECKIFD-NEXT:    ret
110;
111; RV32IZFINXZDINX-LABEL: fmaximum_f64:
112; RV32IZFINXZDINX:       # %bb.0:
113; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
114; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
115; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
116; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
117; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
118; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
119; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
120; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
121; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
122; RV32IZFINXZDINX-NEXT:    feq.d a6, a0, a0
123; RV32IZFINXZDINX-NEXT:    mv a4, a2
124; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB1_2
125; RV32IZFINXZDINX-NEXT:  # %bb.1:
126; RV32IZFINXZDINX-NEXT:    mv a4, a0
127; RV32IZFINXZDINX-NEXT:  .LBB1_2:
128; RV32IZFINXZDINX-NEXT:    feq.d a6, a2, a2
129; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB1_4
130; RV32IZFINXZDINX-NEXT:  # %bb.3:
131; RV32IZFINXZDINX-NEXT:    mv a0, a2
132; RV32IZFINXZDINX-NEXT:  .LBB1_4:
133; RV32IZFINXZDINX-NEXT:    fmax.d a0, a0, a4
134; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
135; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
136; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
137; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
138; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
139; RV32IZFINXZDINX-NEXT:    ret
140;
141; RV64IZFINXZDINX-LABEL: fmaximum_f64:
142; RV64IZFINXZDINX:       # %bb.0:
143; RV64IZFINXZDINX-NEXT:    feq.d a3, a0, a0
144; RV64IZFINXZDINX-NEXT:    mv a2, a1
145; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB1_3
146; RV64IZFINXZDINX-NEXT:  # %bb.1:
147; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
148; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB1_4
149; RV64IZFINXZDINX-NEXT:  .LBB1_2:
150; RV64IZFINXZDINX-NEXT:    fmax.d a0, a0, a2
151; RV64IZFINXZDINX-NEXT:    ret
152; RV64IZFINXZDINX-NEXT:  .LBB1_3:
153; RV64IZFINXZDINX-NEXT:    mv a2, a0
154; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
155; RV64IZFINXZDINX-NEXT:    bnez a3, .LBB1_2
156; RV64IZFINXZDINX-NEXT:  .LBB1_4:
157; RV64IZFINXZDINX-NEXT:    fmax.d a0, a1, a2
158; RV64IZFINXZDINX-NEXT:    ret
159  %1 = call double @llvm.maximum.f64(double %a, double %b)
160  ret double %1
161}
162
163define double @fminimum_nnan_f64(double %a, double %b) nounwind {
164; CHECKIFD-LABEL: fminimum_nnan_f64:
165; CHECKIFD:       # %bb.0:
166; CHECKIFD-NEXT:    fmin.d fa0, fa0, fa1
167; CHECKIFD-NEXT:    ret
168;
169; RV32IZFINXZDINX-LABEL: fminimum_nnan_f64:
170; RV32IZFINXZDINX:       # %bb.0:
171; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
172; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
173; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
174; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
175; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
176; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
177; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
178; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
179; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
180; RV32IZFINXZDINX-NEXT:    fmin.d a0, a0, a2
181; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
182; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
183; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
184; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
185; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
186; RV32IZFINXZDINX-NEXT:    ret
187;
188; RV64IZFINXZDINX-LABEL: fminimum_nnan_f64:
189; RV64IZFINXZDINX:       # %bb.0:
190; RV64IZFINXZDINX-NEXT:    fmin.d a0, a0, a1
191; RV64IZFINXZDINX-NEXT:    ret
192  %1 = call nnan double @llvm.minimum.f64(double %a, double %b)
193  ret double %1
194}
195
196define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
197; CHECKIFD-LABEL: fmaximum_nnan_f64:
198; CHECKIFD:       # %bb.0:
199; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
200; CHECKIFD-NEXT:    fmv.d fa5, fa1
201; CHECKIFD-NEXT:    beqz a0, .LBB3_3
202; CHECKIFD-NEXT:  # %bb.1:
203; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
204; CHECKIFD-NEXT:    beqz a0, .LBB3_4
205; CHECKIFD-NEXT:  .LBB3_2:
206; CHECKIFD-NEXT:    fmin.d fa0, fa0, fa5
207; CHECKIFD-NEXT:    ret
208; CHECKIFD-NEXT:  .LBB3_3:
209; CHECKIFD-NEXT:    fmv.d fa5, fa0
210; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
211; CHECKIFD-NEXT:    bnez a0, .LBB3_2
212; CHECKIFD-NEXT:  .LBB3_4:
213; CHECKIFD-NEXT:    fmin.d fa0, fa1, fa5
214; CHECKIFD-NEXT:    ret
215;
216; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:
217; RV32IZFINXZDINX:       # %bb.0:
218; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
219; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
220; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
221; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
222; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
223; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
224; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
225; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
226; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
227; RV32IZFINXZDINX-NEXT:    feq.d a6, a0, a0
228; RV32IZFINXZDINX-NEXT:    mv a4, a2
229; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB3_2
230; RV32IZFINXZDINX-NEXT:  # %bb.1:
231; RV32IZFINXZDINX-NEXT:    mv a4, a0
232; RV32IZFINXZDINX-NEXT:  .LBB3_2:
233; RV32IZFINXZDINX-NEXT:    feq.d a6, a2, a2
234; RV32IZFINXZDINX-NEXT:    bnez a6, .LBB3_4
235; RV32IZFINXZDINX-NEXT:  # %bb.3:
236; RV32IZFINXZDINX-NEXT:    mv a0, a2
237; RV32IZFINXZDINX-NEXT:  .LBB3_4:
238; RV32IZFINXZDINX-NEXT:    fmin.d a0, a0, a4
239; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
240; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
241; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
242; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
243; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
244; RV32IZFINXZDINX-NEXT:    ret
245;
246; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:
247; RV64IZFINXZDINX:       # %bb.0:
248; RV64IZFINXZDINX-NEXT:    feq.d a3, a0, a0
249; RV64IZFINXZDINX-NEXT:    mv a2, a1
250; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB3_3
251; RV64IZFINXZDINX-NEXT:  # %bb.1:
252; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
253; RV64IZFINXZDINX-NEXT:    beqz a3, .LBB3_4
254; RV64IZFINXZDINX-NEXT:  .LBB3_2:
255; RV64IZFINXZDINX-NEXT:    fmin.d a0, a0, a2
256; RV64IZFINXZDINX-NEXT:    ret
257; RV64IZFINXZDINX-NEXT:  .LBB3_3:
258; RV64IZFINXZDINX-NEXT:    mv a2, a0
259; RV64IZFINXZDINX-NEXT:    feq.d a3, a1, a1
260; RV64IZFINXZDINX-NEXT:    bnez a3, .LBB3_2
261; RV64IZFINXZDINX-NEXT:  .LBB3_4:
262; RV64IZFINXZDINX-NEXT:    fmin.d a0, a1, a2
263; RV64IZFINXZDINX-NEXT:    ret
264  %1 = call double @llvm.minimum.f64(double %a, double %b)
265  ret double %1
266}
267
268define double @fminimum_nnan_op_f64(double %a, double %b) nounwind {
269; CHECKIFD-LABEL: fminimum_nnan_op_f64:
270; CHECKIFD:       # %bb.0:
271; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
272; CHECKIFD-NEXT:    bnez a0, .LBB4_2
273; CHECKIFD-NEXT:  # %bb.1:
274; CHECKIFD-NEXT:    fmin.d fa0, fa1, fa1
275; CHECKIFD-NEXT:    ret
276; CHECKIFD-NEXT:  .LBB4_2:
277; CHECKIFD-NEXT:    fadd.d fa5, fa0, fa0
278; CHECKIFD-NEXT:    fmin.d fa0, fa5, fa1
279; CHECKIFD-NEXT:    ret
280;
281; RV32IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
282; RV32IZFINXZDINX:       # %bb.0:
283; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
284; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
285; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
286; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
287; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
288; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
289; RV32IZFINXZDINX-NEXT:    feq.d a0, a2, a2
290; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
291; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB4_2
292; RV32IZFINXZDINX-NEXT:  # %bb.1:
293; RV32IZFINXZDINX-NEXT:    mv a0, a2
294; RV32IZFINXZDINX-NEXT:    j .LBB4_3
295; RV32IZFINXZDINX-NEXT:  .LBB4_2:
296; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
297; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
298; RV32IZFINXZDINX-NEXT:    fadd.d a0, a0, a0
299; RV32IZFINXZDINX-NEXT:  .LBB4_3:
300; RV32IZFINXZDINX-NEXT:    fmin.d a0, a0, a2
301; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
302; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
303; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
304; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
305; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
306; RV32IZFINXZDINX-NEXT:    ret
307;
308; RV64IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
309; RV64IZFINXZDINX:       # %bb.0:
310; RV64IZFINXZDINX-NEXT:    feq.d a2, a1, a1
311; RV64IZFINXZDINX-NEXT:    bnez a2, .LBB4_2
312; RV64IZFINXZDINX-NEXT:  # %bb.1:
313; RV64IZFINXZDINX-NEXT:    fmin.d a0, a1, a1
314; RV64IZFINXZDINX-NEXT:    ret
315; RV64IZFINXZDINX-NEXT:  .LBB4_2:
316; RV64IZFINXZDINX-NEXT:    fadd.d a0, a0, a0
317; RV64IZFINXZDINX-NEXT:    fmin.d a0, a0, a1
318; RV64IZFINXZDINX-NEXT:    ret
319  %c = fadd nnan double %a, %a
320  %1 = call double @llvm.minimum.f64(double %c, double %b)
321  ret double %1
322}
323
324define double @fmaximum_nnan_op_f64(double %a, double %b) nounwind {
325; CHECKIFD-LABEL: fmaximum_nnan_op_f64:
326; CHECKIFD:       # %bb.0:
327; CHECKIFD-NEXT:    fadd.d fa5, fa0, fa1
328; CHECKIFD-NEXT:    fsub.d fa4, fa0, fa1
329; CHECKIFD-NEXT:    fmax.d fa0, fa5, fa4
330; CHECKIFD-NEXT:    ret
331;
332; RV32IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
333; RV32IZFINXZDINX:       # %bb.0:
334; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
335; RV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
336; RV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
337; RV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
338; RV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
339; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
340; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
341; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
342; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
343; RV32IZFINXZDINX-NEXT:    fadd.d a4, a0, a2
344; RV32IZFINXZDINX-NEXT:    fsub.d a0, a0, a2
345; RV32IZFINXZDINX-NEXT:    fmax.d a0, a4, a0
346; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
347; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
348; RV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
349; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
350; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
351; RV32IZFINXZDINX-NEXT:    ret
352;
353; RV64IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
354; RV64IZFINXZDINX:       # %bb.0:
355; RV64IZFINXZDINX-NEXT:    fadd.d a2, a0, a1
356; RV64IZFINXZDINX-NEXT:    fsub.d a0, a0, a1
357; RV64IZFINXZDINX-NEXT:    fmax.d a0, a2, a0
358; RV64IZFINXZDINX-NEXT:    ret
359  %c = fadd nnan double %a, %b
360  %d = fsub nnan double %a, %b
361  %1 = call double @llvm.maximum.f64(double %c, double %d)
362  ret double %1
363}
364
365;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
366; RV32IFD: {{.*}}
367; RV64IFD: {{.*}}
368