1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4 5define void @foo(i32 %a, ptr %b, i1 %c) nounwind { 6; RV32I-LABEL: foo: 7; RV32I: # %bb.0: 8; RV32I-NEXT: lw a3, 0(a1) 9; RV32I-NEXT: beq a3, a0, .LBB0_14 10; RV32I-NEXT: # %bb.1: # %test2 11; RV32I-NEXT: lw a3, 0(a1) 12; RV32I-NEXT: bne a3, a0, .LBB0_14 13; RV32I-NEXT: # %bb.2: # %test3 14; RV32I-NEXT: lw a3, 0(a1) 15; RV32I-NEXT: blt a3, a0, .LBB0_14 16; RV32I-NEXT: # %bb.3: # %test4 17; RV32I-NEXT: lw a3, 0(a1) 18; RV32I-NEXT: bge a3, a0, .LBB0_14 19; RV32I-NEXT: # %bb.4: # %test5 20; RV32I-NEXT: lw a3, 0(a1) 21; RV32I-NEXT: bltu a3, a0, .LBB0_14 22; RV32I-NEXT: # %bb.5: # %test6 23; RV32I-NEXT: lw a3, 0(a1) 24; RV32I-NEXT: bgeu a3, a0, .LBB0_14 25; RV32I-NEXT: # %bb.6: # %test7 26; RV32I-NEXT: lw a3, 0(a1) 27; RV32I-NEXT: blt a0, a3, .LBB0_14 28; RV32I-NEXT: # %bb.7: # %test8 29; RV32I-NEXT: lw a3, 0(a1) 30; RV32I-NEXT: bge a0, a3, .LBB0_14 31; RV32I-NEXT: # %bb.8: # %test9 32; RV32I-NEXT: lw a3, 0(a1) 33; RV32I-NEXT: bltu a0, a3, .LBB0_14 34; RV32I-NEXT: # %bb.9: # %test10 35; RV32I-NEXT: lw a3, 0(a1) 36; RV32I-NEXT: bgeu a0, a3, .LBB0_14 37; RV32I-NEXT: # %bb.10: # %test11 38; RV32I-NEXT: lw zero, 0(a1) 39; RV32I-NEXT: andi a2, a2, 1 40; RV32I-NEXT: bnez a2, .LBB0_14 41; RV32I-NEXT: # %bb.11: # %test12 42; RV32I-NEXT: lw a0, 0(a1) 43; RV32I-NEXT: bgez a0, .LBB0_14 44; RV32I-NEXT: # %bb.12: # %test13 45; RV32I-NEXT: lw a0, 0(a1) 46; RV32I-NEXT: blez a0, .LBB0_14 47; RV32I-NEXT: # %bb.13: # %test14 48; RV32I-NEXT: lw zero, 0(a1) 49; RV32I-NEXT: .LBB0_14: # %end 50; RV32I-NEXT: ret 51 %val1 = load volatile i32, ptr %b 52 %tst1 = icmp eq i32 %val1, %a 53 br i1 %tst1, label %end, label %test2 54 55test2: 56 %val2 = load volatile i32, ptr %b 57 %tst2 = icmp ne i32 %val2, %a 58 br i1 %tst2, label %end, label %test3 59 60test3: 61 %val3 = load volatile i32, ptr %b 62 %tst3 = icmp slt i32 %val3, %a 63 br i1 %tst3, label %end, label %test4 64 65test4: 66 %val4 = load volatile i32, ptr %b 67 %tst4 = icmp sge i32 %val4, %a 68 br i1 %tst4, label %end, label %test5 69 70test5: 71 %val5 = load volatile i32, ptr %b 72 %tst5 = icmp ult i32 %val5, %a 73 br i1 %tst5, label %end, label %test6 74 75test6: 76 %val6 = load volatile i32, ptr %b 77 %tst6 = icmp uge i32 %val6, %a 78 br i1 %tst6, label %end, label %test7 79 80; Check for condition codes that don't have a matching instruction 81 82test7: 83 %val7 = load volatile i32, ptr %b 84 %tst7 = icmp sgt i32 %val7, %a 85 br i1 %tst7, label %end, label %test8 86 87test8: 88 %val8 = load volatile i32, ptr %b 89 %tst8 = icmp sle i32 %val8, %a 90 br i1 %tst8, label %end, label %test9 91 92test9: 93 %val9 = load volatile i32, ptr %b 94 %tst9 = icmp ugt i32 %val9, %a 95 br i1 %tst9, label %end, label %test10 96 97test10: 98 %val10 = load volatile i32, ptr %b 99 %tst10 = icmp ule i32 %val10, %a 100 br i1 %tst10, label %end, label %test11 101 102; Check the case of a branch where the condition was generated in another 103; function 104 105test11: 106 %val11 = load volatile i32, ptr %b 107 br i1 %c, label %end, label %test12 108 109; Check that we use bgez for X > -1 which is the canonical form. 110 111test12: 112 %val12 = load volatile i32, ptr %b 113 %tst12 = icmp sgt i32 %val12, -1 114 br i1 %tst12, label %end, label %test13 115 116; Check that we use blez (X <= 0) for (X < 1) 117 118test13: 119 %val13 = load volatile i32, ptr %b 120 %tst13 = icmp slt i32 %val13, 1 121 br i1 %tst13, label %end, label %test14 122 123test14: 124 %val14 = load volatile i32, ptr %b 125 br label %end 126 127end: 128 ret void 129} 130