1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2# RUN: llc %s -mtriple=riscv64 -run-pass=peephole-opt -o - | FileCheck %s 3 4# Make sure we shouldn't replace the %2 ADDI with the $x10 ADDI since it has a 5# physical register destination. 6 7--- | 8 define void @foo(i32 signext %0) { 9 tail call void @bar(i32 1) 10 %2 = icmp ugt i32 %0, 1 11 br i1 %2, label %3, label %4 12 13 3: ; preds = %1 14 tail call void @bar(i32 3) 15 ret void 16 17 4: ; preds = %1 18 ret void 19 } 20 21 declare void @bar(...) 22 23... 24--- 25name: foo 26tracksRegLiveness: true 27body: | 28 ; CHECK-LABEL: name: foo 29 ; CHECK: bb.0 (%ir-block.1): 30 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 31 ; CHECK-NEXT: liveins: $x10 32 ; CHECK-NEXT: {{ $}} 33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 34 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 35 ; CHECK-NEXT: $x10 = ADDI $x0, 1 36 ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 37 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 38 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2 39 ; CHECK-NEXT: BLTU [[COPY]], killed [[ADDI]], %bb.2 40 ; CHECK-NEXT: PseudoBR %bb.1 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: bb.1 (%ir-block.3): 43 ; CHECK-NEXT: $x10 = ADDI $x0, 3 44 ; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10 45 ; CHECK-NEXT: {{ $}} 46 ; CHECK-NEXT: bb.2 (%ir-block.4): 47 ; CHECK-NEXT: PseudoRET 48 bb.0 (%ir-block.1): 49 successors: %bb.1, %bb.2 50 liveins: $x10 51 52 %0:gpr = COPY $x10 53 ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 54 $x10 = ADDI $x0, 1 55 PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 56 ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 57 %2:gpr = ADDI $x0, 2 58 BLTU %0, killed %2, %bb.2 59 PseudoBR %bb.1 60 61 bb.1 (%ir-block.3): 62 $x10 = ADDI $x0, 3 63 PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10 64 65 bb.2 (%ir-block.4): 66 PseudoRET 67 68... 69