1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV64I 4 5; Make sure we don't generate an addi in the loop in 6; addition to the addiw. Previously we type legalize the 7; setcc use using signext and the phi use using anyext. 8; We now detect when it would be beneficial to replace 9; anyext with signext. 10 11define void @quux(i32 signext %arg, i32 signext %arg1) nounwind { 12; RV64I-LABEL: quux: 13; RV64I: # %bb.0: # %bb 14; RV64I-NEXT: beq a1, a0, .LBB0_4 15; RV64I-NEXT: # %bb.1: # %bb2.preheader 16; RV64I-NEXT: addi sp, sp, -16 17; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 18; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 19; RV64I-NEXT: subw s0, a1, a0 20; RV64I-NEXT: .LBB0_2: # %bb2 21; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 22; RV64I-NEXT: call hoge 23; RV64I-NEXT: addiw s0, s0, -1 24; RV64I-NEXT: bnez s0, .LBB0_2 25; RV64I-NEXT: # %bb.3: 26; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 27; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 28; RV64I-NEXT: addi sp, sp, 16 29; RV64I-NEXT: .LBB0_4: # %bb6 30; RV64I-NEXT: ret 31bb: 32 %tmp = icmp eq i32 %arg, %arg1 33 br i1 %tmp, label %bb6, label %bb2 34 35bb2: ; preds = %bb2, %bb 36 %tmp3 = phi i32 [ %tmp4, %bb2 ], [ %arg, %bb ] 37 tail call void @hoge() 38 %tmp4 = add nsw i32 %tmp3, 1 39 %tmp5 = icmp eq i32 %tmp4, %arg1 40 br i1 %tmp5, label %bb6, label %bb2 41 42bb6: ; preds = %bb2, %bb 43 ret void 44} 45 46declare void @hoge() 47 48; This ends up creating a shl with a i64 result type, but an i32 shift amount. 49; Because custom type legalization for i32 is enabled, this resulted in 50; LowerOperation being called for the amount. This was not expected and 51; triggered an assert. 52define i32 @crash(i32 signext %x, i32 signext %y, i32 signext %z) { 53; RV64I-LABEL: crash: 54; RV64I: # %bb.0: 55; RV64I-NEXT: seqz a3, a0 56; RV64I-NEXT: addw a0, a1, a2 57; RV64I-NEXT: slli a1, a3, 3 58; RV64I-NEXT: .LBB1_1: # %bb 59; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 60; RV64I-NEXT: beq a0, a1, .LBB1_1 61; RV64I-NEXT: # %bb.2: # %bar 62; RV64I-NEXT: ret 63 br label %bb 64 65bb: 66 %a = icmp eq i32 %x, 0 67 %b = add i32 %y, %z 68 %c = select i1 %a, i32 8, i32 0 69 %d = icmp eq i32 %b, %c 70 br i1 %d, label %bb, label %bar 71 72bar: 73 ret i32 %b 74} 75 76; We prefer to sign extend i32 constants for phis. The default behavior in 77; SelectionDAGBuilder is zero extend. We have a target hook to override it. 78define i64 @sext_phi_constants(i32 signext %c) { 79; RV64I-LABEL: sext_phi_constants: 80; RV64I: # %bb.0: 81; RV64I-NEXT: beqz a0, .LBB2_2 82; RV64I-NEXT: # %bb.1: 83; RV64I-NEXT: li a0, -1 84; RV64I-NEXT: j .LBB2_3 85; RV64I-NEXT: .LBB2_2: # %iffalse 86; RV64I-NEXT: li a0, -2 87; RV64I-NEXT: .LBB2_3: # %merge 88; RV64I-NEXT: slli a0, a0, 32 89; RV64I-NEXT: srli a0, a0, 32 90; RV64I-NEXT: ret 91 %a = icmp ne i32 %c, 0 92 br i1 %a, label %iftrue, label %iffalse 93 94iftrue: 95 br label %merge 96 97iffalse: 98 br label %merge 99 100merge: 101 %b = phi i32 [-1, %iftrue], [-2, %iffalse] 102 %d = zext i32 %b to i64 103 ret i64 %d 104} 105 106; We prefer to sign extend i32 non-negative values. The default behavior in 107; DAGCombiner is zero extend. We have a target hook to override it. 108define signext i32 @square(i32 signext %num) { 109; RV64I-LABEL: square: 110; RV64I: # %bb.0: 111; RV64I-NEXT: mulw a0, a0, a0 112; RV64I-NEXT: ret 113 %mul = mul nsw i32 %num, %num 114 ret i32 %mul 115} 116