xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll (revision d1e17a3f23a30815030b784d813141a469b3d7fb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV32
3; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV64
4
5define i16 @test_lshr_i48(i48 %x) {
6; RV32-LABEL: test_lshr_i48:
7; RV32:       # %bb.0:
8; RV32-NEXT:    srli a0, a0, 16
9; RV32-NEXT:    ret
10;
11; RV64-LABEL: test_lshr_i48:
12; RV64:       # %bb.0:
13; RV64-NEXT:    srliw a0, a0, 16
14; RV64-NEXT:    ret
15  %lshr = lshr i48 %x, 16
16  %trunc = trunc i48 %lshr to i16
17  ret i16 %trunc
18}
19
20define i16 @test_ashr_i48(i48 %x) {
21; RV32-LABEL: test_ashr_i48:
22; RV32:       # %bb.0:
23; RV32-NEXT:    srai a0, a0, 16
24; RV32-NEXT:    ret
25;
26; RV64-LABEL: test_ashr_i48:
27; RV64:       # %bb.0:
28; RV64-NEXT:    sraiw a0, a0, 16
29; RV64-NEXT:    ret
30  %ashr = ashr i48 %x, 16
31  %trunc = trunc i48 %ashr to i16
32  ret i16 %trunc
33}
34
35define i16 @test_shl_i48(i48 %x) {
36; RV32-LABEL: test_shl_i48:
37; RV32:       # %bb.0:
38; RV32-NEXT:    slli a0, a0, 8
39; RV32-NEXT:    ret
40;
41; RV64-LABEL: test_shl_i48:
42; RV64:       # %bb.0:
43; RV64-NEXT:    slli a0, a0, 8
44; RV64-NEXT:    ret
45  %shl = shl i48 %x, 8
46  %trunc = trunc i48 %shl to i16
47  ret i16 %trunc
48}
49
50; FIXME: Could use srlw to remove slli+srli.
51define i16 @test_lshr_i48_2(i48 %x, i48 %y) {
52; RV32-LABEL: test_lshr_i48_2:
53; RV32:       # %bb.0:
54; RV32-NEXT:    andi a2, a2, 15
55; RV32-NEXT:    srl a0, a0, a2
56; RV32-NEXT:    ret
57;
58; RV64-LABEL: test_lshr_i48_2:
59; RV64:       # %bb.0:
60; RV64-NEXT:    andi a1, a1, 15
61; RV64-NEXT:    slli a0, a0, 32
62; RV64-NEXT:    srli a0, a0, 32
63; RV64-NEXT:    srl a0, a0, a1
64; RV64-NEXT:    ret
65  %and = and i48 %y, 15
66  %lshr = lshr i48 %x, %and
67  %trunc = trunc i48 %lshr to i16
68  ret i16 %trunc
69}
70
71; FIXME: Could use sraw to remove the sext.w.
72define i16 @test_ashr_i48_2(i48 %x, i48 %y) {
73; RV32-LABEL: test_ashr_i48_2:
74; RV32:       # %bb.0:
75; RV32-NEXT:    andi a2, a2, 15
76; RV32-NEXT:    sra a0, a0, a2
77; RV32-NEXT:    ret
78;
79; RV64-LABEL: test_ashr_i48_2:
80; RV64:       # %bb.0:
81; RV64-NEXT:    andi a1, a1, 15
82; RV64-NEXT:    sext.w a0, a0
83; RV64-NEXT:    sra a0, a0, a1
84; RV64-NEXT:    ret
85  %and = and i48 %y, 15
86  %ashr = ashr i48 %x, %and
87  %trunc = trunc i48 %ashr to i16
88  ret i16 %trunc
89}
90
91define i16 @test_shl_i48_2(i48 %x, i48 %y) {
92; RV32-LABEL: test_shl_i48_2:
93; RV32:       # %bb.0:
94; RV32-NEXT:    andi a2, a2, 15
95; RV32-NEXT:    sll a0, a0, a2
96; RV32-NEXT:    ret
97;
98; RV64-LABEL: test_shl_i48_2:
99; RV64:       # %bb.0:
100; RV64-NEXT:    andi a1, a1, 15
101; RV64-NEXT:    sll a0, a0, a1
102; RV64-NEXT:    ret
103  %and = and i48 %y, 15
104  %shl = shl i48 %x, %and
105  %trunc = trunc i48 %shl to i16
106  ret i16 %trunc
107}
108