xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/args.ll (revision af8e3861025f3c931cc67ced86d6bd8c939e6fc0) 
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7define void @test_args_i8(i8 %a) {
8
9  ; RV32I-LABEL: name: test_args_i8
10  ; RV32I: bb.1.entry:
11  ; RV32I-NEXT:   liveins: $x10
12  ; RV32I-NEXT: {{  $}}
13  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
14  ; RV32I-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
15  ; RV32I-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
16  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[C]]
17  ; RV32I-NEXT:   PseudoRET
18  ; RV64I-LABEL: name: test_args_i8
19  ; RV64I: bb.1.entry:
20  ; RV64I-NEXT:   liveins: $x10
21  ; RV64I-NEXT: {{  $}}
22  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
23  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
24  ; RV64I-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
25  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[C]]
26  ; RV64I-NEXT:   PseudoRET
27entry:
28  %0 = add i8 %a, 1
29  ret void
30}
31
32define void @test_args_i16(i16 %a) {
33
34  ; RV32I-LABEL: name: test_args_i16
35  ; RV32I: bb.1.entry:
36  ; RV32I-NEXT:   liveins: $x10
37  ; RV32I-NEXT: {{  $}}
38  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
39  ; RV32I-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
40  ; RV32I-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
41  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[C]]
42  ; RV32I-NEXT:   PseudoRET
43  ; RV64I-LABEL: name: test_args_i16
44  ; RV64I: bb.1.entry:
45  ; RV64I-NEXT:   liveins: $x10
46  ; RV64I-NEXT: {{  $}}
47  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
48  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
49  ; RV64I-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
50  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[C]]
51  ; RV64I-NEXT:   PseudoRET
52entry:
53  %0 = add i16 %a, 1
54  ret void
55}
56
57define void @test_args_i32(i32 %a) {
58
59  ; RV32I-LABEL: name: test_args_i32
60  ; RV32I: bb.1.entry:
61  ; RV32I-NEXT:   liveins: $x10
62  ; RV32I-NEXT: {{  $}}
63  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
64  ; RV32I-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
65  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
66  ; RV32I-NEXT:   PseudoRET
67  ; RV64I-LABEL: name: test_args_i32
68  ; RV64I: bb.1.entry:
69  ; RV64I-NEXT:   liveins: $x10
70  ; RV64I-NEXT: {{  $}}
71  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
72  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
73  ; RV64I-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
74  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[C]]
75  ; RV64I-NEXT:   PseudoRET
76entry:
77  %0 = add i32 %a, 1
78  ret void
79}
80
81define void @test_args_i64(i64 %a) {
82
83  ; RV32I-LABEL: name: test_args_i64
84  ; RV32I: bb.1.entry:
85  ; RV32I-NEXT:   liveins: $x10, $x11
86  ; RV32I-NEXT: {{  $}}
87  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
88  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
89  ; RV32I-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
90  ; RV32I-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
91  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[C]]
92  ; RV32I-NEXT:   PseudoRET
93  ; RV64I-LABEL: name: test_args_i64
94  ; RV64I: bb.1.entry:
95  ; RV64I-NEXT:   liveins: $x10
96  ; RV64I-NEXT: {{  $}}
97  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
98  ; RV64I-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
99  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]]
100  ; RV64I-NEXT:   PseudoRET
101entry:
102  %0 = add i64 %a, 1
103  ret void
104}
105
106define void @test_args_i8_ptr(ptr %a) {
107
108  ; RV32I-LABEL: name: test_args_i8_ptr
109  ; RV32I: bb.1.entry:
110  ; RV32I-NEXT:   liveins: $x10
111  ; RV32I-NEXT: {{  $}}
112  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
113  ; RV32I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.a)
114  ; RV32I-NEXT:   PseudoRET
115  ; RV64I-LABEL: name: test_args_i8_ptr
116  ; RV64I: bb.1.entry:
117  ; RV64I-NEXT:   liveins: $x10
118  ; RV64I-NEXT: {{  $}}
119  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
120  ; RV64I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.a)
121  ; RV64I-NEXT:   PseudoRET
122entry:
123  %0 = load i8, ptr %a
124  ret void
125}
126
127define void @test_args_2xi8(i8 %a, i8 %b) {
128
129  ; RV32I-LABEL: name: test_args_2xi8
130  ; RV32I: bb.1.entry:
131  ; RV32I-NEXT:   liveins: $x10, $x11
132  ; RV32I-NEXT: {{  $}}
133  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
134  ; RV32I-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
135  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
136  ; RV32I-NEXT:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
137  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
138  ; RV32I-NEXT:   PseudoRET
139  ; RV64I-LABEL: name: test_args_2xi8
140  ; RV64I: bb.1.entry:
141  ; RV64I-NEXT:   liveins: $x10, $x11
142  ; RV64I-NEXT: {{  $}}
143  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
144  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
145  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
146  ; RV64I-NEXT:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)
147  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
148  ; RV64I-NEXT:   PseudoRET
149entry:
150  %0 = add i8 %a, %b
151  ret void
152}
153
154define void @test_args_2xi16(i16 %a, i16 %b) {
155
156  ; RV32I-LABEL: name: test_args_2xi16
157  ; RV32I: bb.1.entry:
158  ; RV32I-NEXT:   liveins: $x10, $x11
159  ; RV32I-NEXT: {{  $}}
160  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
161  ; RV32I-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
162  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
163  ; RV32I-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
164  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
165  ; RV32I-NEXT:   PseudoRET
166  ; RV64I-LABEL: name: test_args_2xi16
167  ; RV64I: bb.1.entry:
168  ; RV64I-NEXT:   liveins: $x10, $x11
169  ; RV64I-NEXT: {{  $}}
170  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
171  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
172  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
173  ; RV64I-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
174  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
175  ; RV64I-NEXT:   PseudoRET
176entry:
177  %0 = add i16 %a, %b
178  ret void
179}
180
181define void @test_args_2xi32(i32 %a, i32 %b) {
182
183  ; RV32I-LABEL: name: test_args_2xi32
184  ; RV32I: bb.1.entry:
185  ; RV32I-NEXT:   liveins: $x10, $x11
186  ; RV32I-NEXT: {{  $}}
187  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
188  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
189  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
190  ; RV32I-NEXT:   PseudoRET
191  ; RV64I-LABEL: name: test_args_2xi32
192  ; RV64I: bb.1.entry:
193  ; RV64I-NEXT:   liveins: $x10, $x11
194  ; RV64I-NEXT: {{  $}}
195  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
196  ; RV64I-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
197  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
198  ; RV64I-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
199  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
200  ; RV64I-NEXT:   PseudoRET
201entry:
202  %0 = add i32 %a, %b
203  ret void
204}
205
206define void @test_args_2xi64(i64 %a, i64 %b) {
207
208  ; RV32I-LABEL: name: test_args_2xi64
209  ; RV32I: bb.1.entry:
210  ; RV32I-NEXT:   liveins: $x10, $x11, $x12, $x13
211  ; RV32I-NEXT: {{  $}}
212  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10
213  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
214  ; RV32I-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
215  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
216  ; RV32I-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
217  ; RV32I-NEXT:   [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
218  ; RV32I-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[MV1]]
219  ; RV32I-NEXT:   PseudoRET
220  ; RV64I-LABEL: name: test_args_2xi64
221  ; RV64I: bb.1.entry:
222  ; RV64I-NEXT:   liveins: $x10, $x11
223  ; RV64I-NEXT: {{  $}}
224  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10
225  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
226  ; RV64I-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
227  ; RV64I-NEXT:   PseudoRET
228entry:
229  %0 = add i64 %a, %b
230  ret void
231}
232
233define void @test_args_2xi8_ptr(ptr %a, ptr %b) {
234
235  ; RV32I-LABEL: name: test_args_2xi8_ptr
236  ; RV32I: bb.1.entry:
237  ; RV32I-NEXT:   liveins: $x10, $x11
238  ; RV32I-NEXT: {{  $}}
239  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
240  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
241  ; RV32I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.a)
242  ; RV32I-NEXT:   [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.b)
243  ; RV32I-NEXT:   PseudoRET
244  ; RV64I-LABEL: name: test_args_2xi8_ptr
245  ; RV64I: bb.1.entry:
246  ; RV64I-NEXT:   liveins: $x10, $x11
247  ; RV64I-NEXT: {{  $}}
248  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
249  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
250  ; RV64I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.a)
251  ; RV64I-NEXT:   [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.b)
252  ; RV64I-NEXT:   PseudoRET
253entry:
254  %0 = load i8, ptr %a
255  %1 = load i8, ptr %b
256  ret void
257}
258
259define void @test_args_ptr_byval(ptr byval(i8) %a) {
260  ; RV32I-LABEL: name: test_args_ptr_byval
261  ; RV32I: bb.1.entry:
262  ; RV32I-NEXT:   liveins: $x10
263  ; RV32I-NEXT: {{  $}}
264  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
265  ; RV32I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s8) from %ir.a)
266  ; RV32I-NEXT:   PseudoRET
267  ; RV64I-LABEL: name: test_args_ptr_byval
268  ; RV64I: bb.1.entry:
269  ; RV64I-NEXT:   liveins: $x10
270  ; RV64I-NEXT: {{  $}}
271  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
272  ; RV64I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s8) from %ir.a)
273  ; RV64I-NEXT:   PseudoRET
274entry:
275  %0 = load i8, ptr %a
276  ret void
277}
278
279define void @test_args_ptr_sret(ptr sret(i8) %a) {
280  ; RV32I-LABEL: name: test_args_ptr_sret
281  ; RV32I: bb.1.entry:
282  ; RV32I-NEXT:   liveins: $x10
283  ; RV32I-NEXT: {{  $}}
284  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
285  ; RV32I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s8) from %ir.a)
286  ; RV32I-NEXT:   PseudoRET
287  ; RV64I-LABEL: name: test_args_ptr_sret
288  ; RV64I: bb.1.entry:
289  ; RV64I-NEXT:   liveins: $x10
290  ; RV64I-NEXT: {{  $}}
291  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x10
292  ; RV64I-NEXT:   [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s8) from %ir.a)
293  ; RV64I-NEXT:   PseudoRET
294entry:
295  %0 = load i8, ptr %a
296  ret void
297}
298