xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/gisel-commandline-option.ll (revision 8e87dc10b80f298a682bf01fab190a57e6d5af57)
1; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
2; RUN:   -verify-machineinstrs=0 -O0 -global-isel \
3; RUN:   | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O0
4
5; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
6; RUN:   -verify-machineinstrs=0 -global-isel \
7; RUN:   | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O1
8
9; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
10; RUN:   -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \
11; RUN:   | FileCheck %s --check-prefixes=ENABLED,FALLBACK,ENABLED-O1
12
13; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
14; RUN:   -verify-machineinstrs=0 \
15; RUN:   | FileCheck %s --check-prefixes=DISABLED
16
17; ENABLED:       IRTranslator
18; ENABLED-NEXT:  Analysis for ComputingKnownBits
19; ENABLED-O0-NEXT:  RISCVO0PreLegalizerCombiner
20; ENABLED-O1-NEXT:  MachineDominator Tree Construction
21; ENABLED-NEXT:  Analysis containing CSE Info
22; ENABLED-O1-NEXT:  RISCVPreLegalizerCombiner
23; ENABLED-NEXT:  Legalizer
24; ENABLED-O1-NEXT:  MachineDominator Tree Construction
25; ENABLED-O1-NEXT:  RISCVPostLegalizerCombiner
26; ENABLED-NEXT:  RegBankSelect
27; ENABLED-NEXT:  Analysis for ComputingKnownBits
28; ENABLED-O1-NEXT:  Lazy Branch Probability Analysis
29; ENABLED-O1-NEXT:  Lazy Block Frequency Analysis
30; ENABLED-NEXT:  InstructionSelect
31; ENABLED-NEXT:  ResetMachineFunction
32
33; FALLBACK:       RISC-V DAG->DAG Pattern Instruction Selection
34; NOFALLBACK-NOT: RISC-V DAG->DAG Pattern Instruction Selection
35
36; DISABLED-NOT: IRTranslator
37
38; DISABLED: RISC-V DAG->DAG Pattern Instruction Selection
39; DISABLED: Finalize ISel and expand pseudo-instructions
40
41define void @empty() {
42  ret void
43}
44