xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll (revision 115872902b9b056d42e24273f93a2be7c93d2f54) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel -mattr=+f \
3; RUN:   -target-abi=ilp32f \
4; RUN:   | FileCheck -check-prefix=RV32IF %s
5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel -mattr=+d \
6; RUN:   -target-abi=ilp32f \
7; RUN:   | FileCheck -check-prefix=RV32IF %s
8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel -mattr=+f \
9; RUN:   -target-abi=lp64f \
10; RUN:   | FileCheck -check-prefix=RV64IF %s
11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel  -mattr=+d \
12; RUN:   -target-abi=lp64d \
13; RUN:   | FileCheck -check-prefix=RV64IF %s
14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel \
15; RUN:   | FileCheck -check-prefix=RV32I %s
16; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel \
17; RUN:   | FileCheck -check-prefix=RV64I %s
18
19define float @sqrt_f32(float %a) nounwind {
20; RV32IF-LABEL: sqrt_f32:
21; RV32IF:       # %bb.0:
22; RV32IF-NEXT:    fsqrt.s fa0, fa0
23; RV32IF-NEXT:    ret
24;
25; RV64IF-LABEL: sqrt_f32:
26; RV64IF:       # %bb.0:
27; RV64IF-NEXT:    fsqrt.s fa0, fa0
28; RV64IF-NEXT:    ret
29;
30; RV32I-LABEL: sqrt_f32:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    addi sp, sp, -16
33; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
34; RV32I-NEXT:    call sqrtf
35; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
36; RV32I-NEXT:    addi sp, sp, 16
37; RV32I-NEXT:    ret
38;
39; RV64I-LABEL: sqrt_f32:
40; RV64I:       # %bb.0:
41; RV64I-NEXT:    addi sp, sp, -16
42; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
43; RV64I-NEXT:    call sqrtf
44; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
45; RV64I-NEXT:    addi sp, sp, 16
46; RV64I-NEXT:    ret
47  %1 = call float @llvm.sqrt.f32(float %a)
48  ret float %1
49}
50
51define float @powi_f32(float %a, i32 %b) nounwind {
52; RV32IF-LABEL: powi_f32:
53; RV32IF:       # %bb.0:
54; RV32IF-NEXT:    addi sp, sp, -16
55; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
56; RV32IF-NEXT:    call __powisf2
57; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
58; RV32IF-NEXT:    addi sp, sp, 16
59; RV32IF-NEXT:    ret
60;
61; RV64IF-LABEL: powi_f32:
62; RV64IF:       # %bb.0:
63; RV64IF-NEXT:    addi sp, sp, -16
64; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
65; RV64IF-NEXT:    sext.w a0, a0
66; RV64IF-NEXT:    call __powisf2
67; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
68; RV64IF-NEXT:    addi sp, sp, 16
69; RV64IF-NEXT:    ret
70;
71; RV32I-LABEL: powi_f32:
72; RV32I:       # %bb.0:
73; RV32I-NEXT:    addi sp, sp, -16
74; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
75; RV32I-NEXT:    call __powisf2
76; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
77; RV32I-NEXT:    addi sp, sp, 16
78; RV32I-NEXT:    ret
79;
80; RV64I-LABEL: powi_f32:
81; RV64I:       # %bb.0:
82; RV64I-NEXT:    addi sp, sp, -16
83; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
84; RV64I-NEXT:    sext.w a1, a1
85; RV64I-NEXT:    call __powisf2
86; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
87; RV64I-NEXT:    addi sp, sp, 16
88; RV64I-NEXT:    ret
89  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
90  ret float %1
91}
92
93define float @sin_f32(float %a) nounwind {
94; RV32IF-LABEL: sin_f32:
95; RV32IF:       # %bb.0:
96; RV32IF-NEXT:    addi sp, sp, -16
97; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
98; RV32IF-NEXT:    call sinf
99; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
100; RV32IF-NEXT:    addi sp, sp, 16
101; RV32IF-NEXT:    ret
102;
103; RV64IF-LABEL: sin_f32:
104; RV64IF:       # %bb.0:
105; RV64IF-NEXT:    addi sp, sp, -16
106; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
107; RV64IF-NEXT:    call sinf
108; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
109; RV64IF-NEXT:    addi sp, sp, 16
110; RV64IF-NEXT:    ret
111;
112; RV32I-LABEL: sin_f32:
113; RV32I:       # %bb.0:
114; RV32I-NEXT:    addi sp, sp, -16
115; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
116; RV32I-NEXT:    call sinf
117; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
118; RV32I-NEXT:    addi sp, sp, 16
119; RV32I-NEXT:    ret
120;
121; RV64I-LABEL: sin_f32:
122; RV64I:       # %bb.0:
123; RV64I-NEXT:    addi sp, sp, -16
124; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
125; RV64I-NEXT:    call sinf
126; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
127; RV64I-NEXT:    addi sp, sp, 16
128; RV64I-NEXT:    ret
129  %1 = call float @llvm.sin.f32(float %a)
130  ret float %1
131}
132
133define float @cos_f32(float %a) nounwind {
134; RV32IF-LABEL: cos_f32:
135; RV32IF:       # %bb.0:
136; RV32IF-NEXT:    addi sp, sp, -16
137; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
138; RV32IF-NEXT:    call cosf
139; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
140; RV32IF-NEXT:    addi sp, sp, 16
141; RV32IF-NEXT:    ret
142;
143; RV64IF-LABEL: cos_f32:
144; RV64IF:       # %bb.0:
145; RV64IF-NEXT:    addi sp, sp, -16
146; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
147; RV64IF-NEXT:    call cosf
148; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
149; RV64IF-NEXT:    addi sp, sp, 16
150; RV64IF-NEXT:    ret
151;
152; RV32I-LABEL: cos_f32:
153; RV32I:       # %bb.0:
154; RV32I-NEXT:    addi sp, sp, -16
155; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
156; RV32I-NEXT:    call cosf
157; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
158; RV32I-NEXT:    addi sp, sp, 16
159; RV32I-NEXT:    ret
160;
161; RV64I-LABEL: cos_f32:
162; RV64I:       # %bb.0:
163; RV64I-NEXT:    addi sp, sp, -16
164; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
165; RV64I-NEXT:    call cosf
166; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
167; RV64I-NEXT:    addi sp, sp, 16
168; RV64I-NEXT:    ret
169  %1 = call float @llvm.cos.f32(float %a)
170  ret float %1
171}
172
173; The sin+cos combination results in an FSINCOS SelectionDAG node.
174define float @sincos_f32(float %a) nounwind {
175; RV32IF-LABEL: sincos_f32:
176; RV32IF:       # %bb.0:
177; RV32IF-NEXT:    addi sp, sp, -16
178; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
179; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
180; RV32IF-NEXT:    fsw fs1, 4(sp) # 4-byte Folded Spill
181; RV32IF-NEXT:    fmv.s fs0, fa0
182; RV32IF-NEXT:    call sinf
183; RV32IF-NEXT:    fmv.s fs1, fa0
184; RV32IF-NEXT:    fmv.s fa0, fs0
185; RV32IF-NEXT:    call cosf
186; RV32IF-NEXT:    fadd.s fa0, fs1, fa0
187; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
188; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
189; RV32IF-NEXT:    flw fs1, 4(sp) # 4-byte Folded Reload
190; RV32IF-NEXT:    addi sp, sp, 16
191; RV32IF-NEXT:    ret
192;
193; RV32I-LABEL: sincos_f32:
194; RV32I:       # %bb.0:
195; RV32I-NEXT:    addi sp, sp, -16
196; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
197; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
198; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
199; RV32I-NEXT:    mv s0, a0
200; RV32I-NEXT:    call sinf
201; RV32I-NEXT:    mv s1, a0
202; RV32I-NEXT:    mv a0, s0
203; RV32I-NEXT:    call cosf
204; RV32I-NEXT:    mv a1, a0
205; RV32I-NEXT:    mv a0, s1
206; RV32I-NEXT:    call __addsf3
207; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
208; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
209; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
210; RV32I-NEXT:    addi sp, sp, 16
211; RV32I-NEXT:    ret
212;
213; RV64I-LABEL: sincos_f32:
214; RV64I:       # %bb.0:
215; RV64I-NEXT:    addi sp, sp, -32
216; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
217; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
218; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
219; RV64I-NEXT:    mv s0, a0
220; RV64I-NEXT:    call sinf
221; RV64I-NEXT:    mv s1, a0
222; RV64I-NEXT:    mv a0, s0
223; RV64I-NEXT:    call cosf
224; RV64I-NEXT:    mv a1, a0
225; RV64I-NEXT:    mv a0, s1
226; RV64I-NEXT:    call __addsf3
227; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
228; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
229; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
230; RV64I-NEXT:    addi sp, sp, 32
231; RV64I-NEXT:    ret
232  %1 = call float @llvm.sin.f32(float %a)
233  %2 = call float @llvm.cos.f32(float %a)
234  %3 = fadd float %1, %2
235  ret float %3
236}
237
238define float @pow_f32(float %a, float %b) nounwind {
239; RV32IF-LABEL: pow_f32:
240; RV32IF:       # %bb.0:
241; RV32IF-NEXT:    addi sp, sp, -16
242; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
243; RV32IF-NEXT:    call powf
244; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
245; RV32IF-NEXT:    addi sp, sp, 16
246; RV32IF-NEXT:    ret
247;
248; RV64IF-LABEL: pow_f32:
249; RV64IF:       # %bb.0:
250; RV64IF-NEXT:    addi sp, sp, -16
251; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
252; RV64IF-NEXT:    call powf
253; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
254; RV64IF-NEXT:    addi sp, sp, 16
255; RV64IF-NEXT:    ret
256;
257; RV32I-LABEL: pow_f32:
258; RV32I:       # %bb.0:
259; RV32I-NEXT:    addi sp, sp, -16
260; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
261; RV32I-NEXT:    call powf
262; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
263; RV32I-NEXT:    addi sp, sp, 16
264; RV32I-NEXT:    ret
265;
266; RV64I-LABEL: pow_f32:
267; RV64I:       # %bb.0:
268; RV64I-NEXT:    addi sp, sp, -16
269; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
270; RV64I-NEXT:    call powf
271; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
272; RV64I-NEXT:    addi sp, sp, 16
273; RV64I-NEXT:    ret
274  %1 = call float @llvm.pow.f32(float %a, float %b)
275  ret float %1
276}
277
278define float @exp_f32(float %a) nounwind {
279; RV32IF-LABEL: exp_f32:
280; RV32IF:       # %bb.0:
281; RV32IF-NEXT:    addi sp, sp, -16
282; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
283; RV32IF-NEXT:    call expf
284; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
285; RV32IF-NEXT:    addi sp, sp, 16
286; RV32IF-NEXT:    ret
287;
288; RV64IF-LABEL: exp_f32:
289; RV64IF:       # %bb.0:
290; RV64IF-NEXT:    addi sp, sp, -16
291; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
292; RV64IF-NEXT:    call expf
293; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
294; RV64IF-NEXT:    addi sp, sp, 16
295; RV64IF-NEXT:    ret
296;
297; RV32I-LABEL: exp_f32:
298; RV32I:       # %bb.0:
299; RV32I-NEXT:    addi sp, sp, -16
300; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
301; RV32I-NEXT:    call expf
302; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
303; RV32I-NEXT:    addi sp, sp, 16
304; RV32I-NEXT:    ret
305;
306; RV64I-LABEL: exp_f32:
307; RV64I:       # %bb.0:
308; RV64I-NEXT:    addi sp, sp, -16
309; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
310; RV64I-NEXT:    call expf
311; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
312; RV64I-NEXT:    addi sp, sp, 16
313; RV64I-NEXT:    ret
314  %1 = call float @llvm.exp.f32(float %a)
315  ret float %1
316}
317
318define float @exp2_f32(float %a) nounwind {
319; RV32IF-LABEL: exp2_f32:
320; RV32IF:       # %bb.0:
321; RV32IF-NEXT:    addi sp, sp, -16
322; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
323; RV32IF-NEXT:    call exp2f
324; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
325; RV32IF-NEXT:    addi sp, sp, 16
326; RV32IF-NEXT:    ret
327;
328; RV64IF-LABEL: exp2_f32:
329; RV64IF:       # %bb.0:
330; RV64IF-NEXT:    addi sp, sp, -16
331; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
332; RV64IF-NEXT:    call exp2f
333; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
334; RV64IF-NEXT:    addi sp, sp, 16
335; RV64IF-NEXT:    ret
336;
337; RV32I-LABEL: exp2_f32:
338; RV32I:       # %bb.0:
339; RV32I-NEXT:    addi sp, sp, -16
340; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
341; RV32I-NEXT:    call exp2f
342; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
343; RV32I-NEXT:    addi sp, sp, 16
344; RV32I-NEXT:    ret
345;
346; RV64I-LABEL: exp2_f32:
347; RV64I:       # %bb.0:
348; RV64I-NEXT:    addi sp, sp, -16
349; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
350; RV64I-NEXT:    call exp2f
351; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
352; RV64I-NEXT:    addi sp, sp, 16
353; RV64I-NEXT:    ret
354  %1 = call float @llvm.exp2.f32(float %a)
355  ret float %1
356}
357
358define float @exp10_f32(float %a) nounwind {
359; RV32IF-LABEL: exp10_f32:
360; RV32IF:       # %bb.0:
361; RV32IF-NEXT:    addi sp, sp, -16
362; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
363; RV32IF-NEXT:    call exp10f
364; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
365; RV32IF-NEXT:    addi sp, sp, 16
366; RV32IF-NEXT:    ret
367;
368; RV64IF-LABEL: exp10_f32:
369; RV64IF:       # %bb.0:
370; RV64IF-NEXT:    addi sp, sp, -16
371; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
372; RV64IF-NEXT:    call exp10f
373; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
374; RV64IF-NEXT:    addi sp, sp, 16
375; RV64IF-NEXT:    ret
376;
377; RV32I-LABEL: exp10_f32:
378; RV32I:       # %bb.0:
379; RV32I-NEXT:    addi sp, sp, -16
380; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
381; RV32I-NEXT:    call exp10f
382; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
383; RV32I-NEXT:    addi sp, sp, 16
384; RV32I-NEXT:    ret
385;
386; RV64I-LABEL: exp10_f32:
387; RV64I:       # %bb.0:
388; RV64I-NEXT:    addi sp, sp, -16
389; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
390; RV64I-NEXT:    call exp10f
391; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
392; RV64I-NEXT:    addi sp, sp, 16
393; RV64I-NEXT:    ret
394  %1 = call float @llvm.exp10.f32(float %a)
395  ret float %1
396}
397
398define float @log_f32(float %a) nounwind {
399; RV32IF-LABEL: log_f32:
400; RV32IF:       # %bb.0:
401; RV32IF-NEXT:    addi sp, sp, -16
402; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
403; RV32IF-NEXT:    call logf
404; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
405; RV32IF-NEXT:    addi sp, sp, 16
406; RV32IF-NEXT:    ret
407;
408; RV64IF-LABEL: log_f32:
409; RV64IF:       # %bb.0:
410; RV64IF-NEXT:    addi sp, sp, -16
411; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
412; RV64IF-NEXT:    call logf
413; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
414; RV64IF-NEXT:    addi sp, sp, 16
415; RV64IF-NEXT:    ret
416;
417; RV32I-LABEL: log_f32:
418; RV32I:       # %bb.0:
419; RV32I-NEXT:    addi sp, sp, -16
420; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
421; RV32I-NEXT:    call logf
422; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
423; RV32I-NEXT:    addi sp, sp, 16
424; RV32I-NEXT:    ret
425;
426; RV64I-LABEL: log_f32:
427; RV64I:       # %bb.0:
428; RV64I-NEXT:    addi sp, sp, -16
429; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
430; RV64I-NEXT:    call logf
431; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
432; RV64I-NEXT:    addi sp, sp, 16
433; RV64I-NEXT:    ret
434  %1 = call float @llvm.log.f32(float %a)
435  ret float %1
436}
437
438define float @log10_f32(float %a) nounwind {
439; RV32IF-LABEL: log10_f32:
440; RV32IF:       # %bb.0:
441; RV32IF-NEXT:    addi sp, sp, -16
442; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
443; RV32IF-NEXT:    call log10f
444; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
445; RV32IF-NEXT:    addi sp, sp, 16
446; RV32IF-NEXT:    ret
447;
448; RV64IF-LABEL: log10_f32:
449; RV64IF:       # %bb.0:
450; RV64IF-NEXT:    addi sp, sp, -16
451; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
452; RV64IF-NEXT:    call log10f
453; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
454; RV64IF-NEXT:    addi sp, sp, 16
455; RV64IF-NEXT:    ret
456;
457; RV32I-LABEL: log10_f32:
458; RV32I:       # %bb.0:
459; RV32I-NEXT:    addi sp, sp, -16
460; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
461; RV32I-NEXT:    call log10f
462; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
463; RV32I-NEXT:    addi sp, sp, 16
464; RV32I-NEXT:    ret
465;
466; RV64I-LABEL: log10_f32:
467; RV64I:       # %bb.0:
468; RV64I-NEXT:    addi sp, sp, -16
469; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
470; RV64I-NEXT:    call log10f
471; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
472; RV64I-NEXT:    addi sp, sp, 16
473; RV64I-NEXT:    ret
474  %1 = call float @llvm.log10.f32(float %a)
475  ret float %1
476}
477
478define float @log2_f32(float %a) nounwind {
479; RV32IF-LABEL: log2_f32:
480; RV32IF:       # %bb.0:
481; RV32IF-NEXT:    addi sp, sp, -16
482; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
483; RV32IF-NEXT:    call log2f
484; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
485; RV32IF-NEXT:    addi sp, sp, 16
486; RV32IF-NEXT:    ret
487;
488; RV64IF-LABEL: log2_f32:
489; RV64IF:       # %bb.0:
490; RV64IF-NEXT:    addi sp, sp, -16
491; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
492; RV64IF-NEXT:    call log2f
493; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
494; RV64IF-NEXT:    addi sp, sp, 16
495; RV64IF-NEXT:    ret
496;
497; RV32I-LABEL: log2_f32:
498; RV32I:       # %bb.0:
499; RV32I-NEXT:    addi sp, sp, -16
500; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
501; RV32I-NEXT:    call log2f
502; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
503; RV32I-NEXT:    addi sp, sp, 16
504; RV32I-NEXT:    ret
505;
506; RV64I-LABEL: log2_f32:
507; RV64I:       # %bb.0:
508; RV64I-NEXT:    addi sp, sp, -16
509; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
510; RV64I-NEXT:    call log2f
511; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
512; RV64I-NEXT:    addi sp, sp, 16
513; RV64I-NEXT:    ret
514  %1 = call float @llvm.log2.f32(float %a)
515  ret float %1
516}
517
518define float @fma_f32(float %a, float %b, float %c) nounwind {
519; RV32IF-LABEL: fma_f32:
520; RV32IF:       # %bb.0:
521; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
522; RV32IF-NEXT:    ret
523;
524; RV64IF-LABEL: fma_f32:
525; RV64IF:       # %bb.0:
526; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
527; RV64IF-NEXT:    ret
528;
529; RV32I-LABEL: fma_f32:
530; RV32I:       # %bb.0:
531; RV32I-NEXT:    addi sp, sp, -16
532; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
533; RV32I-NEXT:    call fmaf
534; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
535; RV32I-NEXT:    addi sp, sp, 16
536; RV32I-NEXT:    ret
537;
538; RV64I-LABEL: fma_f32:
539; RV64I:       # %bb.0:
540; RV64I-NEXT:    addi sp, sp, -16
541; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
542; RV64I-NEXT:    call fmaf
543; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
544; RV64I-NEXT:    addi sp, sp, 16
545; RV64I-NEXT:    ret
546  %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
547  ret float %1
548}
549
550define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
551; RV32IF-LABEL: fmuladd_f32:
552; RV32IF:       # %bb.0:
553; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
554; RV32IF-NEXT:    ret
555;
556; RV64IF-LABEL: fmuladd_f32:
557; RV64IF:       # %bb.0:
558; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
559; RV64IF-NEXT:    ret
560;
561; RV32I-LABEL: fmuladd_f32:
562; RV32I:       # %bb.0:
563; RV32I-NEXT:    addi sp, sp, -16
564; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
565; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
566; RV32I-NEXT:    mv s0, a2
567; RV32I-NEXT:    call __mulsf3
568; RV32I-NEXT:    mv a1, s0
569; RV32I-NEXT:    call __addsf3
570; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
571; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
572; RV32I-NEXT:    addi sp, sp, 16
573; RV32I-NEXT:    ret
574;
575; RV64I-LABEL: fmuladd_f32:
576; RV64I:       # %bb.0:
577; RV64I-NEXT:    addi sp, sp, -16
578; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
579; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
580; RV64I-NEXT:    mv s0, a2
581; RV64I-NEXT:    call __mulsf3
582; RV64I-NEXT:    mv a1, s0
583; RV64I-NEXT:    call __addsf3
584; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
585; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
586; RV64I-NEXT:    addi sp, sp, 16
587; RV64I-NEXT:    ret
588  %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
589  ret float %1
590}
591
592define float @fabs_f32(float %a) nounwind {
593; RV32IF-LABEL: fabs_f32:
594; RV32IF:       # %bb.0:
595; RV32IF-NEXT:    fabs.s fa0, fa0
596; RV32IF-NEXT:    ret
597;
598; RV64IF-LABEL: fabs_f32:
599; RV64IF:       # %bb.0:
600; RV64IF-NEXT:    fabs.s fa0, fa0
601; RV64IF-NEXT:    ret
602;
603; RV32I-LABEL: fabs_f32:
604; RV32I:       # %bb.0:
605; RV32I-NEXT:    slli a0, a0, 1
606; RV32I-NEXT:    srli a0, a0, 1
607; RV32I-NEXT:    ret
608;
609; RV64I-LABEL: fabs_f32:
610; RV64I:       # %bb.0:
611; RV64I-NEXT:    slli a0, a0, 33
612; RV64I-NEXT:    srli a0, a0, 33
613; RV64I-NEXT:    ret
614  %1 = call float @llvm.fabs.f32(float %a)
615  ret float %1
616}
617
618define float @minnum_f32(float %a, float %b) nounwind {
619; RV32IF-LABEL: minnum_f32:
620; RV32IF:       # %bb.0:
621; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
622; RV32IF-NEXT:    ret
623;
624; RV64IF-LABEL: minnum_f32:
625; RV64IF:       # %bb.0:
626; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
627; RV64IF-NEXT:    ret
628;
629; RV32I-LABEL: minnum_f32:
630; RV32I:       # %bb.0:
631; RV32I-NEXT:    addi sp, sp, -16
632; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
633; RV32I-NEXT:    call fminf
634; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
635; RV32I-NEXT:    addi sp, sp, 16
636; RV32I-NEXT:    ret
637;
638; RV64I-LABEL: minnum_f32:
639; RV64I:       # %bb.0:
640; RV64I-NEXT:    addi sp, sp, -16
641; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
642; RV64I-NEXT:    call fminf
643; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
644; RV64I-NEXT:    addi sp, sp, 16
645; RV64I-NEXT:    ret
646  %1 = call float @llvm.minnum.f32(float %a, float %b)
647  ret float %1
648}
649
650define float @maxnum_f32(float %a, float %b) nounwind {
651; RV32IF-LABEL: maxnum_f32:
652; RV32IF:       # %bb.0:
653; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
654; RV32IF-NEXT:    ret
655;
656; RV64IF-LABEL: maxnum_f32:
657; RV64IF:       # %bb.0:
658; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
659; RV64IF-NEXT:    ret
660;
661; RV32I-LABEL: maxnum_f32:
662; RV32I:       # %bb.0:
663; RV32I-NEXT:    addi sp, sp, -16
664; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
665; RV32I-NEXT:    call fmaxf
666; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
667; RV32I-NEXT:    addi sp, sp, 16
668; RV32I-NEXT:    ret
669;
670; RV64I-LABEL: maxnum_f32:
671; RV64I:       # %bb.0:
672; RV64I-NEXT:    addi sp, sp, -16
673; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
674; RV64I-NEXT:    call fmaxf
675; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
676; RV64I-NEXT:    addi sp, sp, 16
677; RV64I-NEXT:    ret
678  %1 = call float @llvm.maxnum.f32(float %a, float %b)
679  ret float %1
680}
681
682define float @copysign_f32(float %a, float %b) nounwind {
683; RV32IF-LABEL: copysign_f32:
684; RV32IF:       # %bb.0:
685; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
686; RV32IF-NEXT:    ret
687;
688; RV64IF-LABEL: copysign_f32:
689; RV64IF:       # %bb.0:
690; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
691; RV64IF-NEXT:    ret
692;
693; RV32I-LABEL: copysign_f32:
694; RV32I:       # %bb.0:
695; RV32I-NEXT:    lui a2, 524288
696; RV32I-NEXT:    slli a0, a0, 1
697; RV32I-NEXT:    srli a0, a0, 1
698; RV32I-NEXT:    and a1, a1, a2
699; RV32I-NEXT:    or a0, a0, a1
700; RV32I-NEXT:    ret
701;
702; RV64I-LABEL: copysign_f32:
703; RV64I:       # %bb.0:
704; RV64I-NEXT:    lui a2, 524288
705; RV64I-NEXT:    slli a0, a0, 33
706; RV64I-NEXT:    srli a0, a0, 33
707; RV64I-NEXT:    and a1, a1, a2
708; RV64I-NEXT:    or a0, a0, a1
709; RV64I-NEXT:    ret
710  %1 = call float @llvm.copysign.f32(float %a, float %b)
711  ret float %1
712}
713
714define float @ceil_f32(float %a) nounwind {
715; RV32IF-LABEL: ceil_f32:
716; RV32IF:       # %bb.0:
717; RV32IF-NEXT:    addi sp, sp, -16
718; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
719; RV32IF-NEXT:    call ceilf
720; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
721; RV32IF-NEXT:    addi sp, sp, 16
722; RV32IF-NEXT:    ret
723;
724; RV64IF-LABEL: ceil_f32:
725; RV64IF:       # %bb.0:
726; RV64IF-NEXT:    addi sp, sp, -16
727; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
728; RV64IF-NEXT:    call ceilf
729; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
730; RV64IF-NEXT:    addi sp, sp, 16
731; RV64IF-NEXT:    ret
732;
733; RV32I-LABEL: ceil_f32:
734; RV32I:       # %bb.0:
735; RV32I-NEXT:    addi sp, sp, -16
736; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
737; RV32I-NEXT:    call ceilf
738; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
739; RV32I-NEXT:    addi sp, sp, 16
740; RV32I-NEXT:    ret
741;
742; RV64I-LABEL: ceil_f32:
743; RV64I:       # %bb.0:
744; RV64I-NEXT:    addi sp, sp, -16
745; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
746; RV64I-NEXT:    call ceilf
747; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
748; RV64I-NEXT:    addi sp, sp, 16
749; RV64I-NEXT:    ret
750  %1 = call float @llvm.ceil.f32(float %a)
751  ret float %1
752}
753
754define float @trunc_f32(float %a) nounwind {
755; RV32IF-LABEL: trunc_f32:
756; RV32IF:       # %bb.0:
757; RV32IF-NEXT:    addi sp, sp, -16
758; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
759; RV32IF-NEXT:    call truncf
760; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
761; RV32IF-NEXT:    addi sp, sp, 16
762; RV32IF-NEXT:    ret
763;
764; RV64IF-LABEL: trunc_f32:
765; RV64IF:       # %bb.0:
766; RV64IF-NEXT:    addi sp, sp, -16
767; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
768; RV64IF-NEXT:    call truncf
769; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
770; RV64IF-NEXT:    addi sp, sp, 16
771; RV64IF-NEXT:    ret
772;
773; RV32I-LABEL: trunc_f32:
774; RV32I:       # %bb.0:
775; RV32I-NEXT:    addi sp, sp, -16
776; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
777; RV32I-NEXT:    call truncf
778; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
779; RV32I-NEXT:    addi sp, sp, 16
780; RV32I-NEXT:    ret
781;
782; RV64I-LABEL: trunc_f32:
783; RV64I:       # %bb.0:
784; RV64I-NEXT:    addi sp, sp, -16
785; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
786; RV64I-NEXT:    call truncf
787; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
788; RV64I-NEXT:    addi sp, sp, 16
789; RV64I-NEXT:    ret
790  %1 = call float @llvm.trunc.f32(float %a)
791  ret float %1
792}
793
794define float @rint_f32(float %a) nounwind {
795; RV32IF-LABEL: rint_f32:
796; RV32IF:       # %bb.0:
797; RV32IF-NEXT:    addi sp, sp, -16
798; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
799; RV32IF-NEXT:    call rintf
800; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
801; RV32IF-NEXT:    addi sp, sp, 16
802; RV32IF-NEXT:    ret
803;
804; RV64IF-LABEL: rint_f32:
805; RV64IF:       # %bb.0:
806; RV64IF-NEXT:    addi sp, sp, -16
807; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
808; RV64IF-NEXT:    call rintf
809; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
810; RV64IF-NEXT:    addi sp, sp, 16
811; RV64IF-NEXT:    ret
812;
813; RV32I-LABEL: rint_f32:
814; RV32I:       # %bb.0:
815; RV32I-NEXT:    addi sp, sp, -16
816; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
817; RV32I-NEXT:    call rintf
818; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
819; RV32I-NEXT:    addi sp, sp, 16
820; RV32I-NEXT:    ret
821;
822; RV64I-LABEL: rint_f32:
823; RV64I:       # %bb.0:
824; RV64I-NEXT:    addi sp, sp, -16
825; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
826; RV64I-NEXT:    call rintf
827; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
828; RV64I-NEXT:    addi sp, sp, 16
829; RV64I-NEXT:    ret
830  %1 = call float @llvm.rint.f32(float %a)
831  ret float %1
832}
833
834define float @nearbyint_f32(float %a) nounwind {
835; RV32IF-LABEL: nearbyint_f32:
836; RV32IF:       # %bb.0:
837; RV32IF-NEXT:    addi sp, sp, -16
838; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
839; RV32IF-NEXT:    call nearbyintf
840; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
841; RV32IF-NEXT:    addi sp, sp, 16
842; RV32IF-NEXT:    ret
843;
844; RV64IF-LABEL: nearbyint_f32:
845; RV64IF:       # %bb.0:
846; RV64IF-NEXT:    addi sp, sp, -16
847; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
848; RV64IF-NEXT:    call nearbyintf
849; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
850; RV64IF-NEXT:    addi sp, sp, 16
851; RV64IF-NEXT:    ret
852;
853; RV32I-LABEL: nearbyint_f32:
854; RV32I:       # %bb.0:
855; RV32I-NEXT:    addi sp, sp, -16
856; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
857; RV32I-NEXT:    call nearbyintf
858; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
859; RV32I-NEXT:    addi sp, sp, 16
860; RV32I-NEXT:    ret
861;
862; RV64I-LABEL: nearbyint_f32:
863; RV64I:       # %bb.0:
864; RV64I-NEXT:    addi sp, sp, -16
865; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
866; RV64I-NEXT:    call nearbyintf
867; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
868; RV64I-NEXT:    addi sp, sp, 16
869; RV64I-NEXT:    ret
870  %1 = call float @llvm.nearbyint.f32(float %a)
871  ret float %1
872}
873
874define float @round_f32(float %a) nounwind {
875; RV32IF-LABEL: round_f32:
876; RV32IF:       # %bb.0:
877; RV32IF-NEXT:    addi sp, sp, -16
878; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
879; RV32IF-NEXT:    call roundf
880; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
881; RV32IF-NEXT:    addi sp, sp, 16
882; RV32IF-NEXT:    ret
883;
884; RV64IF-LABEL: round_f32:
885; RV64IF:       # %bb.0:
886; RV64IF-NEXT:    addi sp, sp, -16
887; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
888; RV64IF-NEXT:    call roundf
889; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
890; RV64IF-NEXT:    addi sp, sp, 16
891; RV64IF-NEXT:    ret
892;
893; RV32I-LABEL: round_f32:
894; RV32I:       # %bb.0:
895; RV32I-NEXT:    addi sp, sp, -16
896; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
897; RV32I-NEXT:    call roundf
898; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
899; RV32I-NEXT:    addi sp, sp, 16
900; RV32I-NEXT:    ret
901;
902; RV64I-LABEL: round_f32:
903; RV64I:       # %bb.0:
904; RV64I-NEXT:    addi sp, sp, -16
905; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
906; RV64I-NEXT:    call roundf
907; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
908; RV64I-NEXT:    addi sp, sp, 16
909; RV64I-NEXT:    ret
910  %1 = call float @llvm.round.f32(float %a)
911  ret float %1
912}
913
914define float @roundeven_f32(float %a) nounwind {
915; RV32IF-LABEL: roundeven_f32:
916; RV32IF:       # %bb.0:
917; RV32IF-NEXT:    addi sp, sp, -16
918; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
919; RV32IF-NEXT:    call roundevenf
920; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
921; RV32IF-NEXT:    addi sp, sp, 16
922; RV32IF-NEXT:    ret
923;
924; RV64IF-LABEL: roundeven_f32:
925; RV64IF:       # %bb.0:
926; RV64IF-NEXT:    addi sp, sp, -16
927; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
928; RV64IF-NEXT:    call roundevenf
929; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
930; RV64IF-NEXT:    addi sp, sp, 16
931; RV64IF-NEXT:    ret
932;
933; RV32I-LABEL: roundeven_f32:
934; RV32I:       # %bb.0:
935; RV32I-NEXT:    addi sp, sp, -16
936; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
937; RV32I-NEXT:    call roundevenf
938; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
939; RV32I-NEXT:    addi sp, sp, 16
940; RV32I-NEXT:    ret
941;
942; RV64I-LABEL: roundeven_f32:
943; RV64I:       # %bb.0:
944; RV64I-NEXT:    addi sp, sp, -16
945; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
946; RV64I-NEXT:    call roundevenf
947; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
948; RV64I-NEXT:    addi sp, sp, 16
949; RV64I-NEXT:    ret
950  %1 = call float @llvm.roundeven.f32(float %a)
951  ret float %1
952}
953
954define i1 @fpclass(float %x) {
955; RV32IF-LABEL: fpclass:
956; RV32IF:       # %bb.0:
957; RV32IF-NEXT:    fclass.s a0, fa0
958; RV32IF-NEXT:    andi a0, a0, 927
959; RV32IF-NEXT:    snez a0, a0
960; RV32IF-NEXT:    ret
961;
962; RV64IF-LABEL: fpclass:
963; RV64IF:       # %bb.0:
964; RV64IF-NEXT:    fclass.s a0, fa0
965; RV64IF-NEXT:    andi a0, a0, 927
966; RV64IF-NEXT:    snez a0, a0
967; RV64IF-NEXT:    ret
968;
969; RV32I-LABEL: fpclass:
970; RV32I:       # %bb.0:
971; RV32I-NEXT:    lui a1, 522240
972; RV32I-NEXT:    slli a2, a0, 1
973; RV32I-NEXT:    lui a3, 2048
974; RV32I-NEXT:    lui a4, 1046528
975; RV32I-NEXT:    srli a2, a2, 1
976; RV32I-NEXT:    addi a3, a3, -1
977; RV32I-NEXT:    addi a5, a2, -1
978; RV32I-NEXT:    sltu a3, a5, a3
979; RV32I-NEXT:    lui a5, 520192
980; RV32I-NEXT:    xor a0, a0, a2
981; RV32I-NEXT:    add a4, a2, a4
982; RV32I-NEXT:    sltu a4, a4, a5
983; RV32I-NEXT:    xor a5, a2, a1
984; RV32I-NEXT:    sltu a1, a1, a2
985; RV32I-NEXT:    seqz a2, a2
986; RV32I-NEXT:    snez a0, a0
987; RV32I-NEXT:    seqz a5, a5
988; RV32I-NEXT:    and a3, a3, a0
989; RV32I-NEXT:    or a2, a2, a5
990; RV32I-NEXT:    and a0, a4, a0
991; RV32I-NEXT:    or a2, a2, a3
992; RV32I-NEXT:    or a0, a1, a0
993; RV32I-NEXT:    or a0, a2, a0
994; RV32I-NEXT:    ret
995;
996; RV64I-LABEL: fpclass:
997; RV64I:       # %bb.0:
998; RV64I-NEXT:    lui a1, 522240
999; RV64I-NEXT:    slli a2, a0, 33
1000; RV64I-NEXT:    sext.w a0, a0
1001; RV64I-NEXT:    li a3, 1
1002; RV64I-NEXT:    lui a4, 2048
1003; RV64I-NEXT:    lui a5, 520192
1004; RV64I-NEXT:    srli a2, a2, 33
1005; RV64I-NEXT:    addiw a6, a4, -1
1006; RV64I-NEXT:    xor a0, a0, a2
1007; RV64I-NEXT:    subw a3, a2, a3
1008; RV64I-NEXT:    sltu a3, a3, a6
1009; RV64I-NEXT:    xor a6, a2, a1
1010; RV64I-NEXT:    sltu a1, a1, a2
1011; RV64I-NEXT:    subw a4, a2, a4
1012; RV64I-NEXT:    seqz a2, a2
1013; RV64I-NEXT:    snez a0, a0
1014; RV64I-NEXT:    seqz a6, a6
1015; RV64I-NEXT:    sltu a4, a4, a5
1016; RV64I-NEXT:    and a3, a3, a0
1017; RV64I-NEXT:    or a2, a2, a6
1018; RV64I-NEXT:    or a1, a2, a1
1019; RV64I-NEXT:    or a1, a1, a3
1020; RV64I-NEXT:    and a0, a4, a0
1021; RV64I-NEXT:    or a0, a1, a0
1022; RV64I-NEXT:    ret
1023  %cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)
1024  ret i1 %cmp
1025}
1026
1027define i1 @isnan_fpclass(float %x) {
1028; RV32IF-LABEL: isnan_fpclass:
1029; RV32IF:       # %bb.0:
1030; RV32IF-NEXT:    fclass.s a0, fa0
1031; RV32IF-NEXT:    andi a0, a0, 768
1032; RV32IF-NEXT:    snez a0, a0
1033; RV32IF-NEXT:    ret
1034;
1035; RV64IF-LABEL: isnan_fpclass:
1036; RV64IF:       # %bb.0:
1037; RV64IF-NEXT:    fclass.s a0, fa0
1038; RV64IF-NEXT:    andi a0, a0, 768
1039; RV64IF-NEXT:    snez a0, a0
1040; RV64IF-NEXT:    ret
1041;
1042; RV32I-LABEL: isnan_fpclass:
1043; RV32I:       # %bb.0:
1044; RV32I-NEXT:    lui a1, 522240
1045; RV32I-NEXT:    slli a0, a0, 1
1046; RV32I-NEXT:    srli a0, a0, 1
1047; RV32I-NEXT:    sltu a0, a1, a0
1048; RV32I-NEXT:    ret
1049;
1050; RV64I-LABEL: isnan_fpclass:
1051; RV64I:       # %bb.0:
1052; RV64I-NEXT:    lui a1, 522240
1053; RV64I-NEXT:    slli a0, a0, 33
1054; RV64I-NEXT:    srli a0, a0, 33
1055; RV64I-NEXT:    sltu a0, a1, a0
1056; RV64I-NEXT:    ret
1057  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3)  ; nan
1058  ret i1 %1
1059}
1060
1061define i1 @isqnan_fpclass(float %x) {
1062; RV32IF-LABEL: isqnan_fpclass:
1063; RV32IF:       # %bb.0:
1064; RV32IF-NEXT:    fclass.s a0, fa0
1065; RV32IF-NEXT:    andi a0, a0, 512
1066; RV32IF-NEXT:    snez a0, a0
1067; RV32IF-NEXT:    ret
1068;
1069; RV64IF-LABEL: isqnan_fpclass:
1070; RV64IF:       # %bb.0:
1071; RV64IF-NEXT:    fclass.s a0, fa0
1072; RV64IF-NEXT:    andi a0, a0, 512
1073; RV64IF-NEXT:    snez a0, a0
1074; RV64IF-NEXT:    ret
1075;
1076; RV32I-LABEL: isqnan_fpclass:
1077; RV32I:       # %bb.0:
1078; RV32I-NEXT:    slli a0, a0, 1
1079; RV32I-NEXT:    srli a0, a0, 1
1080; RV32I-NEXT:    lui a1, 523264
1081; RV32I-NEXT:    sltu a0, a0, a1
1082; RV32I-NEXT:    xori a0, a0, 1
1083; RV32I-NEXT:    ret
1084;
1085; RV64I-LABEL: isqnan_fpclass:
1086; RV64I:       # %bb.0:
1087; RV64I-NEXT:    slli a0, a0, 33
1088; RV64I-NEXT:    srli a0, a0, 33
1089; RV64I-NEXT:    lui a1, 523264
1090; RV64I-NEXT:    sltu a0, a0, a1
1091; RV64I-NEXT:    xori a0, a0, 1
1092; RV64I-NEXT:    ret
1093  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2)  ; qnan
1094  ret i1 %1
1095}
1096
1097define i1 @issnan_fpclass(float %x) {
1098; RV32IF-LABEL: issnan_fpclass:
1099; RV32IF:       # %bb.0:
1100; RV32IF-NEXT:    fclass.s a0, fa0
1101; RV32IF-NEXT:    andi a0, a0, 256
1102; RV32IF-NEXT:    snez a0, a0
1103; RV32IF-NEXT:    ret
1104;
1105; RV64IF-LABEL: issnan_fpclass:
1106; RV64IF:       # %bb.0:
1107; RV64IF-NEXT:    fclass.s a0, fa0
1108; RV64IF-NEXT:    andi a0, a0, 256
1109; RV64IF-NEXT:    snez a0, a0
1110; RV64IF-NEXT:    ret
1111;
1112; RV32I-LABEL: issnan_fpclass:
1113; RV32I:       # %bb.0:
1114; RV32I-NEXT:    lui a1, 522240
1115; RV32I-NEXT:    slli a0, a0, 1
1116; RV32I-NEXT:    lui a2, 523264
1117; RV32I-NEXT:    srli a0, a0, 1
1118; RV32I-NEXT:    sltu a1, a1, a0
1119; RV32I-NEXT:    sltu a0, a0, a2
1120; RV32I-NEXT:    and a0, a1, a0
1121; RV32I-NEXT:    ret
1122;
1123; RV64I-LABEL: issnan_fpclass:
1124; RV64I:       # %bb.0:
1125; RV64I-NEXT:    lui a1, 522240
1126; RV64I-NEXT:    slli a0, a0, 33
1127; RV64I-NEXT:    lui a2, 523264
1128; RV64I-NEXT:    srli a0, a0, 33
1129; RV64I-NEXT:    sltu a1, a1, a0
1130; RV64I-NEXT:    sltu a0, a0, a2
1131; RV64I-NEXT:    and a0, a1, a0
1132; RV64I-NEXT:    ret
1133  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1)  ; snan
1134  ret i1 %1
1135}
1136
1137define i1 @isinf_fpclass(float %x) {
1138; RV32IF-LABEL: isinf_fpclass:
1139; RV32IF:       # %bb.0:
1140; RV32IF-NEXT:    fclass.s a0, fa0
1141; RV32IF-NEXT:    andi a0, a0, 129
1142; RV32IF-NEXT:    snez a0, a0
1143; RV32IF-NEXT:    ret
1144;
1145; RV64IF-LABEL: isinf_fpclass:
1146; RV64IF:       # %bb.0:
1147; RV64IF-NEXT:    fclass.s a0, fa0
1148; RV64IF-NEXT:    andi a0, a0, 129
1149; RV64IF-NEXT:    snez a0, a0
1150; RV64IF-NEXT:    ret
1151;
1152; RV32I-LABEL: isinf_fpclass:
1153; RV32I:       # %bb.0:
1154; RV32I-NEXT:    lui a1, 522240
1155; RV32I-NEXT:    slli a0, a0, 1
1156; RV32I-NEXT:    srli a0, a0, 1
1157; RV32I-NEXT:    xor a0, a0, a1
1158; RV32I-NEXT:    seqz a0, a0
1159; RV32I-NEXT:    ret
1160;
1161; RV64I-LABEL: isinf_fpclass:
1162; RV64I:       # %bb.0:
1163; RV64I-NEXT:    lui a1, 522240
1164; RV64I-NEXT:    slli a0, a0, 33
1165; RV64I-NEXT:    srli a0, a0, 33
1166; RV64I-NEXT:    xor a0, a0, a1
1167; RV64I-NEXT:    seqz a0, a0
1168; RV64I-NEXT:    ret
1169  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516)  ; 0x204 = "inf"
1170  ret i1 %1
1171}
1172
1173define i1 @isposinf_fpclass(float %x) {
1174; RV32IF-LABEL: isposinf_fpclass:
1175; RV32IF:       # %bb.0:
1176; RV32IF-NEXT:    fclass.s a0, fa0
1177; RV32IF-NEXT:    andi a0, a0, 128
1178; RV32IF-NEXT:    snez a0, a0
1179; RV32IF-NEXT:    ret
1180;
1181; RV64IF-LABEL: isposinf_fpclass:
1182; RV64IF:       # %bb.0:
1183; RV64IF-NEXT:    fclass.s a0, fa0
1184; RV64IF-NEXT:    andi a0, a0, 128
1185; RV64IF-NEXT:    snez a0, a0
1186; RV64IF-NEXT:    ret
1187;
1188; RV32I-LABEL: isposinf_fpclass:
1189; RV32I:       # %bb.0:
1190; RV32I-NEXT:    lui a1, 522240
1191; RV32I-NEXT:    xor a0, a0, a1
1192; RV32I-NEXT:    seqz a0, a0
1193; RV32I-NEXT:    ret
1194;
1195; RV64I-LABEL: isposinf_fpclass:
1196; RV64I:       # %bb.0:
1197; RV64I-NEXT:    lui a1, 522240
1198; RV64I-NEXT:    sext.w a0, a0
1199; RV64I-NEXT:    xor a0, a0, a1
1200; RV64I-NEXT:    seqz a0, a0
1201; RV64I-NEXT:    ret
1202  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 512)  ; 0x200 = "+inf"
1203  ret i1 %1
1204}
1205
1206define i1 @isneginf_fpclass(float %x) {
1207; RV32IF-LABEL: isneginf_fpclass:
1208; RV32IF:       # %bb.0:
1209; RV32IF-NEXT:    fclass.s a0, fa0
1210; RV32IF-NEXT:    andi a0, a0, 1
1211; RV32IF-NEXT:    snez a0, a0
1212; RV32IF-NEXT:    ret
1213;
1214; RV64IF-LABEL: isneginf_fpclass:
1215; RV64IF:       # %bb.0:
1216; RV64IF-NEXT:    fclass.s a0, fa0
1217; RV64IF-NEXT:    andi a0, a0, 1
1218; RV64IF-NEXT:    snez a0, a0
1219; RV64IF-NEXT:    ret
1220;
1221; RV32I-LABEL: isneginf_fpclass:
1222; RV32I:       # %bb.0:
1223; RV32I-NEXT:    lui a1, 1046528
1224; RV32I-NEXT:    xor a0, a0, a1
1225; RV32I-NEXT:    seqz a0, a0
1226; RV32I-NEXT:    ret
1227;
1228; RV64I-LABEL: isneginf_fpclass:
1229; RV64I:       # %bb.0:
1230; RV64I-NEXT:    lui a1, 1046528
1231; RV64I-NEXT:    sext.w a0, a0
1232; RV64I-NEXT:    xor a0, a0, a1
1233; RV64I-NEXT:    seqz a0, a0
1234; RV64I-NEXT:    ret
1235  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 4)  ; "-inf"
1236  ret i1 %1
1237}
1238
1239define i1 @isfinite_fpclass(float %x) {
1240; RV32IF-LABEL: isfinite_fpclass:
1241; RV32IF:       # %bb.0:
1242; RV32IF-NEXT:    fclass.s a0, fa0
1243; RV32IF-NEXT:    andi a0, a0, 126
1244; RV32IF-NEXT:    snez a0, a0
1245; RV32IF-NEXT:    ret
1246;
1247; RV64IF-LABEL: isfinite_fpclass:
1248; RV64IF:       # %bb.0:
1249; RV64IF-NEXT:    fclass.s a0, fa0
1250; RV64IF-NEXT:    andi a0, a0, 126
1251; RV64IF-NEXT:    snez a0, a0
1252; RV64IF-NEXT:    ret
1253;
1254; RV32I-LABEL: isfinite_fpclass:
1255; RV32I:       # %bb.0:
1256; RV32I-NEXT:    lui a1, 522240
1257; RV32I-NEXT:    slli a0, a0, 1
1258; RV32I-NEXT:    srli a0, a0, 1
1259; RV32I-NEXT:    sltu a0, a0, a1
1260; RV32I-NEXT:    ret
1261;
1262; RV64I-LABEL: isfinite_fpclass:
1263; RV64I:       # %bb.0:
1264; RV64I-NEXT:    lui a1, 522240
1265; RV64I-NEXT:    slli a0, a0, 33
1266; RV64I-NEXT:    srli a0, a0, 33
1267; RV64I-NEXT:    sltu a0, a0, a1
1268; RV64I-NEXT:    ret
1269  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504)  ; 0x1f8 = "finite"
1270  ret i1 %1
1271}
1272
1273define i1 @isposfinite_fpclass(float %x) {
1274; RV32IF-LABEL: isposfinite_fpclass:
1275; RV32IF:       # %bb.0:
1276; RV32IF-NEXT:    fclass.s a0, fa0
1277; RV32IF-NEXT:    andi a0, a0, 112
1278; RV32IF-NEXT:    snez a0, a0
1279; RV32IF-NEXT:    ret
1280;
1281; RV64IF-LABEL: isposfinite_fpclass:
1282; RV64IF:       # %bb.0:
1283; RV64IF-NEXT:    fclass.s a0, fa0
1284; RV64IF-NEXT:    andi a0, a0, 112
1285; RV64IF-NEXT:    snez a0, a0
1286; RV64IF-NEXT:    ret
1287;
1288; RV32I-LABEL: isposfinite_fpclass:
1289; RV32I:       # %bb.0:
1290; RV32I-NEXT:    lui a1, 522240
1291; RV32I-NEXT:    sltu a0, a0, a1
1292; RV32I-NEXT:    ret
1293;
1294; RV64I-LABEL: isposfinite_fpclass:
1295; RV64I:       # %bb.0:
1296; RV64I-NEXT:    lui a1, 522240
1297; RV64I-NEXT:    sext.w a0, a0
1298; RV64I-NEXT:    sltu a0, a0, a1
1299; RV64I-NEXT:    ret
1300  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448)  ; 0x1c0 = "+finite"
1301  ret i1 %1
1302}
1303
1304define i1 @isnegfinite_fpclass(float %x) {
1305; RV32IF-LABEL: isnegfinite_fpclass:
1306; RV32IF:       # %bb.0:
1307; RV32IF-NEXT:    fclass.s a0, fa0
1308; RV32IF-NEXT:    andi a0, a0, 14
1309; RV32IF-NEXT:    snez a0, a0
1310; RV32IF-NEXT:    ret
1311;
1312; RV64IF-LABEL: isnegfinite_fpclass:
1313; RV64IF:       # %bb.0:
1314; RV64IF-NEXT:    fclass.s a0, fa0
1315; RV64IF-NEXT:    andi a0, a0, 14
1316; RV64IF-NEXT:    snez a0, a0
1317; RV64IF-NEXT:    ret
1318;
1319; RV32I-LABEL: isnegfinite_fpclass:
1320; RV32I:       # %bb.0:
1321; RV32I-NEXT:    lui a1, 522240
1322; RV32I-NEXT:    slli a2, a0, 1
1323; RV32I-NEXT:    srli a2, a2, 1
1324; RV32I-NEXT:    xor a0, a0, a2
1325; RV32I-NEXT:    snez a0, a0
1326; RV32I-NEXT:    sltu a1, a2, a1
1327; RV32I-NEXT:    and a0, a1, a0
1328; RV32I-NEXT:    ret
1329;
1330; RV64I-LABEL: isnegfinite_fpclass:
1331; RV64I:       # %bb.0:
1332; RV64I-NEXT:    lui a1, 522240
1333; RV64I-NEXT:    slli a2, a0, 33
1334; RV64I-NEXT:    sext.w a0, a0
1335; RV64I-NEXT:    srli a2, a2, 33
1336; RV64I-NEXT:    xor a0, a0, a2
1337; RV64I-NEXT:    snez a0, a0
1338; RV64I-NEXT:    sltu a1, a2, a1
1339; RV64I-NEXT:    and a0, a1, a0
1340; RV64I-NEXT:    ret
1341  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56)  ; 0x38 = "-finite"
1342  ret i1 %1
1343}
1344
1345define i1 @isnotfinite_fpclass(float %x) {
1346; RV32IF-LABEL: isnotfinite_fpclass:
1347; RV32IF:       # %bb.0:
1348; RV32IF-NEXT:    fclass.s a0, fa0
1349; RV32IF-NEXT:    andi a0, a0, 897
1350; RV32IF-NEXT:    snez a0, a0
1351; RV32IF-NEXT:    ret
1352;
1353; RV64IF-LABEL: isnotfinite_fpclass:
1354; RV64IF:       # %bb.0:
1355; RV64IF-NEXT:    fclass.s a0, fa0
1356; RV64IF-NEXT:    andi a0, a0, 897
1357; RV64IF-NEXT:    snez a0, a0
1358; RV64IF-NEXT:    ret
1359;
1360; RV32I-LABEL: isnotfinite_fpclass:
1361; RV32I:       # %bb.0:
1362; RV32I-NEXT:    lui a1, 522240
1363; RV32I-NEXT:    slli a0, a0, 1
1364; RV32I-NEXT:    srli a0, a0, 1
1365; RV32I-NEXT:    xor a2, a0, a1
1366; RV32I-NEXT:    seqz a2, a2
1367; RV32I-NEXT:    sltu a0, a1, a0
1368; RV32I-NEXT:    or a0, a2, a0
1369; RV32I-NEXT:    ret
1370;
1371; RV64I-LABEL: isnotfinite_fpclass:
1372; RV64I:       # %bb.0:
1373; RV64I-NEXT:    lui a1, 522240
1374; RV64I-NEXT:    slli a0, a0, 33
1375; RV64I-NEXT:    srli a0, a0, 33
1376; RV64I-NEXT:    xor a2, a0, a1
1377; RV64I-NEXT:    seqz a2, a2
1378; RV64I-NEXT:    sltu a0, a1, a0
1379; RV64I-NEXT:    or a0, a2, a0
1380; RV64I-NEXT:    ret
1381  %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519)  ; ox207 = "inf|nan"
1382  ret i1 %1
1383}
1384
1385define float @tan_f32(float %a) nounwind {
1386; RV32IF-LABEL: tan_f32:
1387; RV32IF:       # %bb.0:
1388; RV32IF-NEXT:    addi sp, sp, -16
1389; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1390; RV32IF-NEXT:    call tanf
1391; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1392; RV32IF-NEXT:    addi sp, sp, 16
1393; RV32IF-NEXT:    ret
1394;
1395; RV64IF-LABEL: tan_f32:
1396; RV64IF:       # %bb.0:
1397; RV64IF-NEXT:    addi sp, sp, -16
1398; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1399; RV64IF-NEXT:    call tanf
1400; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1401; RV64IF-NEXT:    addi sp, sp, 16
1402; RV64IF-NEXT:    ret
1403;
1404; RV32I-LABEL: tan_f32:
1405; RV32I:       # %bb.0:
1406; RV32I-NEXT:    addi sp, sp, -16
1407; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1408; RV32I-NEXT:    call tanf
1409; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1410; RV32I-NEXT:    addi sp, sp, 16
1411; RV32I-NEXT:    ret
1412;
1413; RV64I-LABEL: tan_f32:
1414; RV64I:       # %bb.0:
1415; RV64I-NEXT:    addi sp, sp, -16
1416; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1417; RV64I-NEXT:    call tanf
1418; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1419; RV64I-NEXT:    addi sp, sp, 16
1420; RV64I-NEXT:    ret
1421  %1 = call float @llvm.tan.f32(float %a)
1422  ret float %1
1423}
1424
1425define float @ldexp_float(float %x, i32 %y) nounwind {
1426; RV32IF-LABEL: ldexp_float:
1427; RV32IF:       # %bb.0:
1428; RV32IF-NEXT:    addi sp, sp, -16
1429; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1430; RV32IF-NEXT:    call ldexpf
1431; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1432; RV32IF-NEXT:    addi sp, sp, 16
1433; RV32IF-NEXT:    ret
1434;
1435; RV64IF-LABEL: ldexp_float:
1436; RV64IF:       # %bb.0:
1437; RV64IF-NEXT:    addi sp, sp, -16
1438; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1439; RV64IF-NEXT:    sext.w a0, a0
1440; RV64IF-NEXT:    call ldexpf
1441; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1442; RV64IF-NEXT:    addi sp, sp, 16
1443; RV64IF-NEXT:    ret
1444;
1445; RV32I-LABEL: ldexp_float:
1446; RV32I:       # %bb.0:
1447; RV32I-NEXT:    addi sp, sp, -16
1448; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1449; RV32I-NEXT:    call ldexpf
1450; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1451; RV32I-NEXT:    addi sp, sp, 16
1452; RV32I-NEXT:    ret
1453;
1454; RV64I-LABEL: ldexp_float:
1455; RV64I:       # %bb.0:
1456; RV64I-NEXT:    addi sp, sp, -16
1457; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1458; RV64I-NEXT:    sext.w a1, a1
1459; RV64I-NEXT:    call ldexpf
1460; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1461; RV64I-NEXT:    addi sp, sp, 16
1462; RV64I-NEXT:    ret
1463  %z = call float @llvm.ldexp.f32.i32(float %x, i32 %y)
1464  ret float %z
1465}
1466
1467define float @asin_f32(float %a) nounwind {
1468; RV32IF-LABEL: asin_f32:
1469; RV32IF:       # %bb.0:
1470; RV32IF-NEXT:    addi sp, sp, -16
1471; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1472; RV32IF-NEXT:    call asinf
1473; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1474; RV32IF-NEXT:    addi sp, sp, 16
1475; RV32IF-NEXT:    ret
1476;
1477; RV64IF-LABEL: asin_f32:
1478; RV64IF:       # %bb.0:
1479; RV64IF-NEXT:    addi sp, sp, -16
1480; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1481; RV64IF-NEXT:    call asinf
1482; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1483; RV64IF-NEXT:    addi sp, sp, 16
1484; RV64IF-NEXT:    ret
1485;
1486; RV32I-LABEL: asin_f32:
1487; RV32I:       # %bb.0:
1488; RV32I-NEXT:    addi sp, sp, -16
1489; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1490; RV32I-NEXT:    call asinf
1491; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1492; RV32I-NEXT:    addi sp, sp, 16
1493; RV32I-NEXT:    ret
1494;
1495; RV64I-LABEL: asin_f32:
1496; RV64I:       # %bb.0:
1497; RV64I-NEXT:    addi sp, sp, -16
1498; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1499; RV64I-NEXT:    call asinf
1500; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1501; RV64I-NEXT:    addi sp, sp, 16
1502; RV64I-NEXT:    ret
1503  %1 = call float @llvm.asin.f32(float %a)
1504  ret float %1
1505}
1506
1507define float @acos_f32(float %a) nounwind {
1508; RV32IF-LABEL: acos_f32:
1509; RV32IF:       # %bb.0:
1510; RV32IF-NEXT:    addi sp, sp, -16
1511; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1512; RV32IF-NEXT:    call acosf
1513; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1514; RV32IF-NEXT:    addi sp, sp, 16
1515; RV32IF-NEXT:    ret
1516;
1517; RV64IF-LABEL: acos_f32:
1518; RV64IF:       # %bb.0:
1519; RV64IF-NEXT:    addi sp, sp, -16
1520; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1521; RV64IF-NEXT:    call acosf
1522; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1523; RV64IF-NEXT:    addi sp, sp, 16
1524; RV64IF-NEXT:    ret
1525;
1526; RV32I-LABEL: acos_f32:
1527; RV32I:       # %bb.0:
1528; RV32I-NEXT:    addi sp, sp, -16
1529; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1530; RV32I-NEXT:    call acosf
1531; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1532; RV32I-NEXT:    addi sp, sp, 16
1533; RV32I-NEXT:    ret
1534;
1535; RV64I-LABEL: acos_f32:
1536; RV64I:       # %bb.0:
1537; RV64I-NEXT:    addi sp, sp, -16
1538; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1539; RV64I-NEXT:    call acosf
1540; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1541; RV64I-NEXT:    addi sp, sp, 16
1542; RV64I-NEXT:    ret
1543  %1 = call float @llvm.acos.f32(float %a)
1544  ret float %1
1545}
1546
1547define float @atan_f32(float %a) nounwind {
1548; RV32IF-LABEL: atan_f32:
1549; RV32IF:       # %bb.0:
1550; RV32IF-NEXT:    addi sp, sp, -16
1551; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1552; RV32IF-NEXT:    call atanf
1553; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1554; RV32IF-NEXT:    addi sp, sp, 16
1555; RV32IF-NEXT:    ret
1556;
1557; RV64IF-LABEL: atan_f32:
1558; RV64IF:       # %bb.0:
1559; RV64IF-NEXT:    addi sp, sp, -16
1560; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1561; RV64IF-NEXT:    call atanf
1562; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1563; RV64IF-NEXT:    addi sp, sp, 16
1564; RV64IF-NEXT:    ret
1565;
1566; RV32I-LABEL: atan_f32:
1567; RV32I:       # %bb.0:
1568; RV32I-NEXT:    addi sp, sp, -16
1569; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1570; RV32I-NEXT:    call atanf
1571; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1572; RV32I-NEXT:    addi sp, sp, 16
1573; RV32I-NEXT:    ret
1574;
1575; RV64I-LABEL: atan_f32:
1576; RV64I:       # %bb.0:
1577; RV64I-NEXT:    addi sp, sp, -16
1578; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1579; RV64I-NEXT:    call atanf
1580; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1581; RV64I-NEXT:    addi sp, sp, 16
1582; RV64I-NEXT:    ret
1583  %1 = call float @llvm.atan.f32(float %a)
1584  ret float %1
1585}
1586
1587define float @atan2_f32(float %a, float %b) nounwind {
1588; RV32IF-LABEL: atan2_f32:
1589; RV32IF:       # %bb.0:
1590; RV32IF-NEXT:    addi sp, sp, -16
1591; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1592; RV32IF-NEXT:    call atan2f
1593; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1594; RV32IF-NEXT:    addi sp, sp, 16
1595; RV32IF-NEXT:    ret
1596;
1597; RV64IF-LABEL: atan2_f32:
1598; RV64IF:       # %bb.0:
1599; RV64IF-NEXT:    addi sp, sp, -16
1600; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1601; RV64IF-NEXT:    call atan2f
1602; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1603; RV64IF-NEXT:    addi sp, sp, 16
1604; RV64IF-NEXT:    ret
1605;
1606; RV32I-LABEL: atan2_f32:
1607; RV32I:       # %bb.0:
1608; RV32I-NEXT:    addi sp, sp, -16
1609; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1610; RV32I-NEXT:    call atan2f
1611; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1612; RV32I-NEXT:    addi sp, sp, 16
1613; RV32I-NEXT:    ret
1614;
1615; RV64I-LABEL: atan2_f32:
1616; RV64I:       # %bb.0:
1617; RV64I-NEXT:    addi sp, sp, -16
1618; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1619; RV64I-NEXT:    call atan2f
1620; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1621; RV64I-NEXT:    addi sp, sp, 16
1622; RV64I-NEXT:    ret
1623  %1 = call float @llvm.atan2.f32(float %a, float %b)
1624  ret float %1
1625}
1626
1627define float @sinh_f32(float %a) nounwind {
1628; RV32IF-LABEL: sinh_f32:
1629; RV32IF:       # %bb.0:
1630; RV32IF-NEXT:    addi sp, sp, -16
1631; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1632; RV32IF-NEXT:    call sinhf
1633; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1634; RV32IF-NEXT:    addi sp, sp, 16
1635; RV32IF-NEXT:    ret
1636;
1637; RV64IF-LABEL: sinh_f32:
1638; RV64IF:       # %bb.0:
1639; RV64IF-NEXT:    addi sp, sp, -16
1640; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1641; RV64IF-NEXT:    call sinhf
1642; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1643; RV64IF-NEXT:    addi sp, sp, 16
1644; RV64IF-NEXT:    ret
1645;
1646; RV32I-LABEL: sinh_f32:
1647; RV32I:       # %bb.0:
1648; RV32I-NEXT:    addi sp, sp, -16
1649; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1650; RV32I-NEXT:    call sinhf
1651; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1652; RV32I-NEXT:    addi sp, sp, 16
1653; RV32I-NEXT:    ret
1654;
1655; RV64I-LABEL: sinh_f32:
1656; RV64I:       # %bb.0:
1657; RV64I-NEXT:    addi sp, sp, -16
1658; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1659; RV64I-NEXT:    call sinhf
1660; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1661; RV64I-NEXT:    addi sp, sp, 16
1662; RV64I-NEXT:    ret
1663  %1 = call float @llvm.sinh.f32(float %a)
1664  ret float %1
1665}
1666
1667define float @cosh_f32(float %a) nounwind {
1668; RV32IF-LABEL: cosh_f32:
1669; RV32IF:       # %bb.0:
1670; RV32IF-NEXT:    addi sp, sp, -16
1671; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1672; RV32IF-NEXT:    call coshf
1673; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1674; RV32IF-NEXT:    addi sp, sp, 16
1675; RV32IF-NEXT:    ret
1676;
1677; RV64IF-LABEL: cosh_f32:
1678; RV64IF:       # %bb.0:
1679; RV64IF-NEXT:    addi sp, sp, -16
1680; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1681; RV64IF-NEXT:    call coshf
1682; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1683; RV64IF-NEXT:    addi sp, sp, 16
1684; RV64IF-NEXT:    ret
1685;
1686; RV32I-LABEL: cosh_f32:
1687; RV32I:       # %bb.0:
1688; RV32I-NEXT:    addi sp, sp, -16
1689; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1690; RV32I-NEXT:    call coshf
1691; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1692; RV32I-NEXT:    addi sp, sp, 16
1693; RV32I-NEXT:    ret
1694;
1695; RV64I-LABEL: cosh_f32:
1696; RV64I:       # %bb.0:
1697; RV64I-NEXT:    addi sp, sp, -16
1698; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1699; RV64I-NEXT:    call coshf
1700; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1701; RV64I-NEXT:    addi sp, sp, 16
1702; RV64I-NEXT:    ret
1703  %1 = call float @llvm.cosh.f32(float %a)
1704  ret float %1
1705}
1706
1707define float @tanh_f32(float %a) nounwind {
1708; RV32IF-LABEL: tanh_f32:
1709; RV32IF:       # %bb.0:
1710; RV32IF-NEXT:    addi sp, sp, -16
1711; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1712; RV32IF-NEXT:    call tanhf
1713; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1714; RV32IF-NEXT:    addi sp, sp, 16
1715; RV32IF-NEXT:    ret
1716;
1717; RV64IF-LABEL: tanh_f32:
1718; RV64IF:       # %bb.0:
1719; RV64IF-NEXT:    addi sp, sp, -16
1720; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1721; RV64IF-NEXT:    call tanhf
1722; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1723; RV64IF-NEXT:    addi sp, sp, 16
1724; RV64IF-NEXT:    ret
1725;
1726; RV32I-LABEL: tanh_f32:
1727; RV32I:       # %bb.0:
1728; RV32I-NEXT:    addi sp, sp, -16
1729; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1730; RV32I-NEXT:    call tanhf
1731; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1732; RV32I-NEXT:    addi sp, sp, 16
1733; RV32I-NEXT:    ret
1734;
1735; RV64I-LABEL: tanh_f32:
1736; RV64I:       # %bb.0:
1737; RV64I-NEXT:    addi sp, sp, -16
1738; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1739; RV64I-NEXT:    call tanhf
1740; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1741; RV64I-NEXT:    addi sp, sp, 16
1742; RV64I-NEXT:    ret
1743  %1 = call float @llvm.tanh.f32(float %a)
1744  ret float %1
1745}
1746