xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll (revision 115872902b9b056d42e24273f93a2be7c93d2f54) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
6; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define float @fcvt_s_d(double %a) nounwind {
12; CHECKIFD-LABEL: fcvt_s_d:
13; CHECKIFD:       # %bb.0:
14; CHECKIFD-NEXT:    fcvt.s.d fa0, fa0
15; CHECKIFD-NEXT:    ret
16;
17; RV32I-LABEL: fcvt_s_d:
18; RV32I:       # %bb.0:
19; RV32I-NEXT:    addi sp, sp, -16
20; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
21; RV32I-NEXT:    call __truncdfsf2
22; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
23; RV32I-NEXT:    addi sp, sp, 16
24; RV32I-NEXT:    ret
25;
26; RV64I-LABEL: fcvt_s_d:
27; RV64I:       # %bb.0:
28; RV64I-NEXT:    addi sp, sp, -16
29; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
30; RV64I-NEXT:    call __truncdfsf2
31; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
32; RV64I-NEXT:    addi sp, sp, 16
33; RV64I-NEXT:    ret
34  %1 = fptrunc double %a to float
35  ret float %1
36}
37
38define double @fcvt_d_s(float %a) nounwind {
39; CHECKIFD-LABEL: fcvt_d_s:
40; CHECKIFD:       # %bb.0:
41; CHECKIFD-NEXT:    fcvt.d.s fa0, fa0
42; CHECKIFD-NEXT:    ret
43;
44; RV32I-LABEL: fcvt_d_s:
45; RV32I:       # %bb.0:
46; RV32I-NEXT:    addi sp, sp, -16
47; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
48; RV32I-NEXT:    call __extendsfdf2
49; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
50; RV32I-NEXT:    addi sp, sp, 16
51; RV32I-NEXT:    ret
52;
53; RV64I-LABEL: fcvt_d_s:
54; RV64I:       # %bb.0:
55; RV64I-NEXT:    addi sp, sp, -16
56; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
57; RV64I-NEXT:    call __extendsfdf2
58; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
59; RV64I-NEXT:    addi sp, sp, 16
60; RV64I-NEXT:    ret
61  %1 = fpext float %a to double
62  ret double %1
63}
64
65define i32 @fcvt_w_d(double %a) nounwind {
66; CHECKIFD-LABEL: fcvt_w_d:
67; CHECKIFD:       # %bb.0:
68; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
69; CHECKIFD-NEXT:    ret
70;
71; RV32I-LABEL: fcvt_w_d:
72; RV32I:       # %bb.0:
73; RV32I-NEXT:    addi sp, sp, -16
74; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
75; RV32I-NEXT:    call __fixdfsi
76; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
77; RV32I-NEXT:    addi sp, sp, 16
78; RV32I-NEXT:    ret
79;
80; RV64I-LABEL: fcvt_w_d:
81; RV64I:       # %bb.0:
82; RV64I-NEXT:    addi sp, sp, -16
83; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
84; RV64I-NEXT:    call __fixdfsi
85; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
86; RV64I-NEXT:    addi sp, sp, 16
87; RV64I-NEXT:    ret
88  %1 = fptosi double %a to i32
89  ret i32 %1
90}
91
92define i32 @fcvt_wu_d(double %a) nounwind {
93; CHECKIFD-LABEL: fcvt_wu_d:
94; CHECKIFD:       # %bb.0:
95; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
96; CHECKIFD-NEXT:    ret
97;
98; RV32I-LABEL: fcvt_wu_d:
99; RV32I:       # %bb.0:
100; RV32I-NEXT:    addi sp, sp, -16
101; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
102; RV32I-NEXT:    call __fixunsdfsi
103; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
104; RV32I-NEXT:    addi sp, sp, 16
105; RV32I-NEXT:    ret
106;
107; RV64I-LABEL: fcvt_wu_d:
108; RV64I:       # %bb.0:
109; RV64I-NEXT:    addi sp, sp, -16
110; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
111; RV64I-NEXT:    call __fixunsdfsi
112; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
113; RV64I-NEXT:    addi sp, sp, 16
114; RV64I-NEXT:    ret
115  %1 = fptoui double %a to i32
116  ret i32 %1
117}
118
119define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
120; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
121; CHECKIFD:       # %bb.0:
122; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
123; CHECKIFD-NEXT:    bnez a0, .LBB4_2
124; CHECKIFD-NEXT:  # %bb.1:
125; CHECKIFD-NEXT:    li a0, 1
126; CHECKIFD-NEXT:  .LBB4_2:
127; CHECKIFD-NEXT:    ret
128;
129; RV32I-LABEL: fcvt_wu_d_multiple_use:
130; RV32I:       # %bb.0:
131; RV32I-NEXT:    addi sp, sp, -16
132; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
133; RV32I-NEXT:    call __fixunsdfsi
134; RV32I-NEXT:    bnez a0, .LBB4_2
135; RV32I-NEXT:  # %bb.1:
136; RV32I-NEXT:    li a0, 1
137; RV32I-NEXT:  .LBB4_2:
138; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
139; RV32I-NEXT:    addi sp, sp, 16
140; RV32I-NEXT:    ret
141;
142; RV64I-LABEL: fcvt_wu_d_multiple_use:
143; RV64I:       # %bb.0:
144; RV64I-NEXT:    addi sp, sp, -16
145; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
146; RV64I-NEXT:    call __fixunsdfsi
147; RV64I-NEXT:    sext.w a1, a0
148; RV64I-NEXT:    bnez a1, .LBB4_2
149; RV64I-NEXT:  # %bb.1:
150; RV64I-NEXT:    li a0, 1
151; RV64I-NEXT:  .LBB4_2:
152; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
153; RV64I-NEXT:    addi sp, sp, 16
154; RV64I-NEXT:    ret
155  %a = fptoui double %x to i32
156  %b = icmp eq i32 %a, 0
157  %c = select i1 %b, i32 1, i32 %a
158  ret i32 %c
159}
160
161define double @fcvt_d_w(i32 %a) nounwind {
162; CHECKIFD-LABEL: fcvt_d_w:
163; CHECKIFD:       # %bb.0:
164; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
165; CHECKIFD-NEXT:    ret
166;
167; RV32I-LABEL: fcvt_d_w:
168; RV32I:       # %bb.0:
169; RV32I-NEXT:    addi sp, sp, -16
170; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
171; RV32I-NEXT:    call __floatsidf
172; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
173; RV32I-NEXT:    addi sp, sp, 16
174; RV32I-NEXT:    ret
175;
176; RV64I-LABEL: fcvt_d_w:
177; RV64I:       # %bb.0:
178; RV64I-NEXT:    addi sp, sp, -16
179; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
180; RV64I-NEXT:    sext.w a0, a0
181; RV64I-NEXT:    call __floatsidf
182; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
183; RV64I-NEXT:    addi sp, sp, 16
184; RV64I-NEXT:    ret
185  %1 = sitofp i32 %a to double
186  ret double %1
187}
188
189define double @fcvt_d_w_load(ptr %p) nounwind {
190; CHECKIFD-LABEL: fcvt_d_w_load:
191; CHECKIFD:       # %bb.0:
192; CHECKIFD-NEXT:    lw a0, 0(a0)
193; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
194; CHECKIFD-NEXT:    ret
195;
196; RV32I-LABEL: fcvt_d_w_load:
197; RV32I:       # %bb.0:
198; RV32I-NEXT:    addi sp, sp, -16
199; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
200; RV32I-NEXT:    lw a0, 0(a0)
201; RV32I-NEXT:    call __floatsidf
202; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
203; RV32I-NEXT:    addi sp, sp, 16
204; RV32I-NEXT:    ret
205;
206; RV64I-LABEL: fcvt_d_w_load:
207; RV64I:       # %bb.0:
208; RV64I-NEXT:    addi sp, sp, -16
209; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
210; RV64I-NEXT:    lw a0, 0(a0)
211; RV64I-NEXT:    call __floatsidf
212; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
213; RV64I-NEXT:    addi sp, sp, 16
214; RV64I-NEXT:    ret
215  %a = load i32, ptr %p
216  %1 = sitofp i32 %a to double
217  ret double %1
218}
219
220define double @fcvt_d_wu(i32 %a) nounwind {
221; CHECKIFD-LABEL: fcvt_d_wu:
222; CHECKIFD:       # %bb.0:
223; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
224; CHECKIFD-NEXT:    ret
225;
226; RV32I-LABEL: fcvt_d_wu:
227; RV32I:       # %bb.0:
228; RV32I-NEXT:    addi sp, sp, -16
229; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
230; RV32I-NEXT:    call __floatunsidf
231; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
232; RV32I-NEXT:    addi sp, sp, 16
233; RV32I-NEXT:    ret
234;
235; RV64I-LABEL: fcvt_d_wu:
236; RV64I:       # %bb.0:
237; RV64I-NEXT:    addi sp, sp, -16
238; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
239; RV64I-NEXT:    sext.w a0, a0
240; RV64I-NEXT:    call __floatunsidf
241; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
242; RV64I-NEXT:    addi sp, sp, 16
243; RV64I-NEXT:    ret
244  %1 = uitofp i32 %a to double
245  ret double %1
246}
247
248define double @fcvt_d_wu_load(ptr %p) nounwind {
249; RV32IFD-LABEL: fcvt_d_wu_load:
250; RV32IFD:       # %bb.0:
251; RV32IFD-NEXT:    lw a0, 0(a0)
252; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
253; RV32IFD-NEXT:    ret
254;
255; RV64IFD-LABEL: fcvt_d_wu_load:
256; RV64IFD:       # %bb.0:
257; RV64IFD-NEXT:    lwu a0, 0(a0)
258; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
259; RV64IFD-NEXT:    ret
260;
261; RV32I-LABEL: fcvt_d_wu_load:
262; RV32I:       # %bb.0:
263; RV32I-NEXT:    addi sp, sp, -16
264; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
265; RV32I-NEXT:    lw a0, 0(a0)
266; RV32I-NEXT:    call __floatunsidf
267; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
268; RV32I-NEXT:    addi sp, sp, 16
269; RV32I-NEXT:    ret
270;
271; RV64I-LABEL: fcvt_d_wu_load:
272; RV64I:       # %bb.0:
273; RV64I-NEXT:    addi sp, sp, -16
274; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
275; RV64I-NEXT:    lw a0, 0(a0)
276; RV64I-NEXT:    call __floatunsidf
277; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
278; RV64I-NEXT:    addi sp, sp, 16
279; RV64I-NEXT:    ret
280  %a = load i32, ptr %p
281  %1 = uitofp i32 %a to double
282  ret double %1
283}
284
285define i64 @fcvt_l_d(double %a) nounwind {
286; RV32IFD-LABEL: fcvt_l_d:
287; RV32IFD:       # %bb.0:
288; RV32IFD-NEXT:    addi sp, sp, -16
289; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
290; RV32IFD-NEXT:    call __fixdfdi
291; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
292; RV32IFD-NEXT:    addi sp, sp, 16
293; RV32IFD-NEXT:    ret
294;
295; RV64IFD-LABEL: fcvt_l_d:
296; RV64IFD:       # %bb.0:
297; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
298; RV64IFD-NEXT:    ret
299;
300; RV32I-LABEL: fcvt_l_d:
301; RV32I:       # %bb.0:
302; RV32I-NEXT:    addi sp, sp, -16
303; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
304; RV32I-NEXT:    call __fixdfdi
305; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
306; RV32I-NEXT:    addi sp, sp, 16
307; RV32I-NEXT:    ret
308;
309; RV64I-LABEL: fcvt_l_d:
310; RV64I:       # %bb.0:
311; RV64I-NEXT:    addi sp, sp, -16
312; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
313; RV64I-NEXT:    call __fixdfdi
314; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
315; RV64I-NEXT:    addi sp, sp, 16
316; RV64I-NEXT:    ret
317  %1 = fptosi double %a to i64
318  ret i64 %1
319}
320
321define i64 @fcvt_lu_d(double %a) nounwind {
322; RV32IFD-LABEL: fcvt_lu_d:
323; RV32IFD:       # %bb.0:
324; RV32IFD-NEXT:    addi sp, sp, -16
325; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
326; RV32IFD-NEXT:    call __fixunsdfdi
327; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
328; RV32IFD-NEXT:    addi sp, sp, 16
329; RV32IFD-NEXT:    ret
330;
331; RV64IFD-LABEL: fcvt_lu_d:
332; RV64IFD:       # %bb.0:
333; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
334; RV64IFD-NEXT:    ret
335;
336; RV32I-LABEL: fcvt_lu_d:
337; RV32I:       # %bb.0:
338; RV32I-NEXT:    addi sp, sp, -16
339; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
340; RV32I-NEXT:    call __fixunsdfdi
341; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
342; RV32I-NEXT:    addi sp, sp, 16
343; RV32I-NEXT:    ret
344;
345; RV64I-LABEL: fcvt_lu_d:
346; RV64I:       # %bb.0:
347; RV64I-NEXT:    addi sp, sp, -16
348; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
349; RV64I-NEXT:    call __fixunsdfdi
350; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
351; RV64I-NEXT:    addi sp, sp, 16
352; RV64I-NEXT:    ret
353  %1 = fptoui double %a to i64
354  ret i64 %1
355}
356
357define i64 @fmv_x_d(double %a, double %b) nounwind {
358; RV32IFD-LABEL: fmv_x_d:
359; RV32IFD:       # %bb.0:
360; RV32IFD-NEXT:    addi sp, sp, -16
361; RV32IFD-NEXT:    fadd.d fa5, fa0, fa1
362; RV32IFD-NEXT:    fsd fa5, 8(sp)
363; RV32IFD-NEXT:    lw a0, 8(sp)
364; RV32IFD-NEXT:    lw a1, 12(sp)
365; RV32IFD-NEXT:    addi sp, sp, 16
366; RV32IFD-NEXT:    ret
367;
368; RV64IFD-LABEL: fmv_x_d:
369; RV64IFD:       # %bb.0:
370; RV64IFD-NEXT:    fadd.d fa5, fa0, fa1
371; RV64IFD-NEXT:    fmv.x.d a0, fa5
372; RV64IFD-NEXT:    ret
373;
374; RV32I-LABEL: fmv_x_d:
375; RV32I:       # %bb.0:
376; RV32I-NEXT:    addi sp, sp, -16
377; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
378; RV32I-NEXT:    call __adddf3
379; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
380; RV32I-NEXT:    addi sp, sp, 16
381; RV32I-NEXT:    ret
382;
383; RV64I-LABEL: fmv_x_d:
384; RV64I:       # %bb.0:
385; RV64I-NEXT:    addi sp, sp, -16
386; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
387; RV64I-NEXT:    call __adddf3
388; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
389; RV64I-NEXT:    addi sp, sp, 16
390; RV64I-NEXT:    ret
391  %1 = fadd double %a, %b
392  %2 = bitcast double %1 to i64
393  ret i64 %2
394}
395
396define double @fcvt_d_l(i64 %a) nounwind {
397; RV32IFD-LABEL: fcvt_d_l:
398; RV32IFD:       # %bb.0:
399; RV32IFD-NEXT:    addi sp, sp, -16
400; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
401; RV32IFD-NEXT:    call __floatdidf
402; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
403; RV32IFD-NEXT:    addi sp, sp, 16
404; RV32IFD-NEXT:    ret
405;
406; RV64IFD-LABEL: fcvt_d_l:
407; RV64IFD:       # %bb.0:
408; RV64IFD-NEXT:    fcvt.d.l fa0, a0
409; RV64IFD-NEXT:    ret
410;
411; RV32I-LABEL: fcvt_d_l:
412; RV32I:       # %bb.0:
413; RV32I-NEXT:    addi sp, sp, -16
414; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
415; RV32I-NEXT:    call __floatdidf
416; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
417; RV32I-NEXT:    addi sp, sp, 16
418; RV32I-NEXT:    ret
419;
420; RV64I-LABEL: fcvt_d_l:
421; RV64I:       # %bb.0:
422; RV64I-NEXT:    addi sp, sp, -16
423; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
424; RV64I-NEXT:    call __floatdidf
425; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
426; RV64I-NEXT:    addi sp, sp, 16
427; RV64I-NEXT:    ret
428  %1 = sitofp i64 %a to double
429  ret double %1
430}
431
432define double @fcvt_d_lu(i64 %a) nounwind {
433; RV32IFD-LABEL: fcvt_d_lu:
434; RV32IFD:       # %bb.0:
435; RV32IFD-NEXT:    addi sp, sp, -16
436; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
437; RV32IFD-NEXT:    call __floatundidf
438; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
439; RV32IFD-NEXT:    addi sp, sp, 16
440; RV32IFD-NEXT:    ret
441;
442; RV64IFD-LABEL: fcvt_d_lu:
443; RV64IFD:       # %bb.0:
444; RV64IFD-NEXT:    fcvt.d.lu fa0, a0
445; RV64IFD-NEXT:    ret
446;
447; RV32I-LABEL: fcvt_d_lu:
448; RV32I:       # %bb.0:
449; RV32I-NEXT:    addi sp, sp, -16
450; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
451; RV32I-NEXT:    call __floatundidf
452; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
453; RV32I-NEXT:    addi sp, sp, 16
454; RV32I-NEXT:    ret
455;
456; RV64I-LABEL: fcvt_d_lu:
457; RV64I:       # %bb.0:
458; RV64I-NEXT:    addi sp, sp, -16
459; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
460; RV64I-NEXT:    call __floatundidf
461; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
462; RV64I-NEXT:    addi sp, sp, 16
463; RV64I-NEXT:    ret
464  %1 = uitofp i64 %a to double
465  ret double %1
466}
467
468define double @fmv_d_x(i64 %a, i64 %b) nounwind {
469; RV32IFD-LABEL: fmv_d_x:
470; RV32IFD:       # %bb.0:
471; RV32IFD-NEXT:    addi sp, sp, -16
472; RV32IFD-NEXT:    sw a0, 8(sp)
473; RV32IFD-NEXT:    sw a1, 12(sp)
474; RV32IFD-NEXT:    fld fa5, 8(sp)
475; RV32IFD-NEXT:    sw a2, 8(sp)
476; RV32IFD-NEXT:    sw a3, 12(sp)
477; RV32IFD-NEXT:    fld fa4, 8(sp)
478; RV32IFD-NEXT:    fadd.d fa0, fa5, fa4
479; RV32IFD-NEXT:    addi sp, sp, 16
480; RV32IFD-NEXT:    ret
481;
482; RV64IFD-LABEL: fmv_d_x:
483; RV64IFD:       # %bb.0:
484; RV64IFD-NEXT:    fmv.d.x fa5, a0
485; RV64IFD-NEXT:    fmv.d.x fa4, a1
486; RV64IFD-NEXT:    fadd.d fa0, fa5, fa4
487; RV64IFD-NEXT:    ret
488;
489; RV32I-LABEL: fmv_d_x:
490; RV32I:       # %bb.0:
491; RV32I-NEXT:    addi sp, sp, -16
492; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
493; RV32I-NEXT:    call __adddf3
494; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
495; RV32I-NEXT:    addi sp, sp, 16
496; RV32I-NEXT:    ret
497;
498; RV64I-LABEL: fmv_d_x:
499; RV64I:       # %bb.0:
500; RV64I-NEXT:    addi sp, sp, -16
501; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
502; RV64I-NEXT:    call __adddf3
503; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
504; RV64I-NEXT:    addi sp, sp, 16
505; RV64I-NEXT:    ret
506  %1 = bitcast i64 %a to double
507  %2 = bitcast i64 %b to double
508  %3 = fadd double %1, %2
509  ret double %3
510}
511
512define double @fcvt_d_w_i8(i8 signext %a) nounwind {
513; CHECKIFD-LABEL: fcvt_d_w_i8:
514; CHECKIFD:       # %bb.0:
515; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
516; CHECKIFD-NEXT:    ret
517;
518; RV32I-LABEL: fcvt_d_w_i8:
519; RV32I:       # %bb.0:
520; RV32I-NEXT:    addi sp, sp, -16
521; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
522; RV32I-NEXT:    call __floatsidf
523; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
524; RV32I-NEXT:    addi sp, sp, 16
525; RV32I-NEXT:    ret
526;
527; RV64I-LABEL: fcvt_d_w_i8:
528; RV64I:       # %bb.0:
529; RV64I-NEXT:    addi sp, sp, -16
530; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
531; RV64I-NEXT:    call __floatsidf
532; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
533; RV64I-NEXT:    addi sp, sp, 16
534; RV64I-NEXT:    ret
535  %1 = sitofp i8 %a to double
536  ret double %1
537}
538
539define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
540; CHECKIFD-LABEL: fcvt_d_wu_i8:
541; CHECKIFD:       # %bb.0:
542; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
543; CHECKIFD-NEXT:    ret
544;
545; RV32I-LABEL: fcvt_d_wu_i8:
546; RV32I:       # %bb.0:
547; RV32I-NEXT:    addi sp, sp, -16
548; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
549; RV32I-NEXT:    call __floatunsidf
550; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
551; RV32I-NEXT:    addi sp, sp, 16
552; RV32I-NEXT:    ret
553;
554; RV64I-LABEL: fcvt_d_wu_i8:
555; RV64I:       # %bb.0:
556; RV64I-NEXT:    addi sp, sp, -16
557; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
558; RV64I-NEXT:    call __floatunsidf
559; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
560; RV64I-NEXT:    addi sp, sp, 16
561; RV64I-NEXT:    ret
562  %1 = uitofp i8 %a to double
563  ret double %1
564}
565
566define double @fcvt_d_w_i16(i16 signext %a) nounwind {
567; CHECKIFD-LABEL: fcvt_d_w_i16:
568; CHECKIFD:       # %bb.0:
569; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
570; CHECKIFD-NEXT:    ret
571;
572; RV32I-LABEL: fcvt_d_w_i16:
573; RV32I:       # %bb.0:
574; RV32I-NEXT:    addi sp, sp, -16
575; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
576; RV32I-NEXT:    call __floatsidf
577; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
578; RV32I-NEXT:    addi sp, sp, 16
579; RV32I-NEXT:    ret
580;
581; RV64I-LABEL: fcvt_d_w_i16:
582; RV64I:       # %bb.0:
583; RV64I-NEXT:    addi sp, sp, -16
584; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
585; RV64I-NEXT:    call __floatsidf
586; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
587; RV64I-NEXT:    addi sp, sp, 16
588; RV64I-NEXT:    ret
589  %1 = sitofp i16 %a to double
590  ret double %1
591}
592
593define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
594; CHECKIFD-LABEL: fcvt_d_wu_i16:
595; CHECKIFD:       # %bb.0:
596; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
597; CHECKIFD-NEXT:    ret
598;
599; RV32I-LABEL: fcvt_d_wu_i16:
600; RV32I:       # %bb.0:
601; RV32I-NEXT:    addi sp, sp, -16
602; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
603; RV32I-NEXT:    call __floatunsidf
604; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
605; RV32I-NEXT:    addi sp, sp, 16
606; RV32I-NEXT:    ret
607;
608; RV64I-LABEL: fcvt_d_wu_i16:
609; RV64I:       # %bb.0:
610; RV64I-NEXT:    addi sp, sp, -16
611; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
612; RV64I-NEXT:    call __floatunsidf
613; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
614; RV64I-NEXT:    addi sp, sp, 16
615; RV64I-NEXT:    ret
616  %1 = uitofp i16 %a to double
617  ret double %1
618}
619
620define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
621; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
622; RV32IFD:       # %bb.0:
623; RV32IFD-NEXT:    addi a0, a0, 1
624; RV32IFD-NEXT:    fcvt.d.w fa5, a0
625; RV32IFD-NEXT:    fsd fa5, 0(a1)
626; RV32IFD-NEXT:    ret
627;
628; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
629; RV64IFD:       # %bb.0:
630; RV64IFD-NEXT:    addiw a0, a0, 1
631; RV64IFD-NEXT:    fcvt.d.w fa5, a0
632; RV64IFD-NEXT:    fsd fa5, 0(a1)
633; RV64IFD-NEXT:    ret
634;
635; RV32I-LABEL: fcvt_d_w_demanded_bits:
636; RV32I:       # %bb.0:
637; RV32I-NEXT:    addi sp, sp, -16
638; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
639; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
640; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
641; RV32I-NEXT:    mv s0, a1
642; RV32I-NEXT:    addi s1, a0, 1
643; RV32I-NEXT:    mv a0, s1
644; RV32I-NEXT:    call __floatsidf
645; RV32I-NEXT:    sw a0, 0(s0)
646; RV32I-NEXT:    sw a1, 4(s0)
647; RV32I-NEXT:    mv a0, s1
648; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
649; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
650; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
651; RV32I-NEXT:    addi sp, sp, 16
652; RV32I-NEXT:    ret
653;
654; RV64I-LABEL: fcvt_d_w_demanded_bits:
655; RV64I:       # %bb.0:
656; RV64I-NEXT:    addi sp, sp, -32
657; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
658; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
659; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
660; RV64I-NEXT:    mv s0, a1
661; RV64I-NEXT:    addiw s1, a0, 1
662; RV64I-NEXT:    mv a0, s1
663; RV64I-NEXT:    call __floatsidf
664; RV64I-NEXT:    sd a0, 0(s0)
665; RV64I-NEXT:    mv a0, s1
666; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
667; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
668; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
669; RV64I-NEXT:    addi sp, sp, 32
670; RV64I-NEXT:    ret
671  %3 = add i32 %0, 1
672  %4 = sitofp i32 %3 to double
673  store double %4, ptr %1, align 8
674  ret i32 %3
675}
676
677define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
678; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
679; RV32IFD:       # %bb.0:
680; RV32IFD-NEXT:    addi a0, a0, 1
681; RV32IFD-NEXT:    fcvt.d.wu fa5, a0
682; RV32IFD-NEXT:    fsd fa5, 0(a1)
683; RV32IFD-NEXT:    ret
684;
685; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
686; RV64IFD:       # %bb.0:
687; RV64IFD-NEXT:    addiw a0, a0, 1
688; RV64IFD-NEXT:    fcvt.d.wu fa5, a0
689; RV64IFD-NEXT:    fsd fa5, 0(a1)
690; RV64IFD-NEXT:    ret
691;
692; RV32I-LABEL: fcvt_d_wu_demanded_bits:
693; RV32I:       # %bb.0:
694; RV32I-NEXT:    addi sp, sp, -16
695; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
696; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
697; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
698; RV32I-NEXT:    mv s0, a1
699; RV32I-NEXT:    addi s1, a0, 1
700; RV32I-NEXT:    mv a0, s1
701; RV32I-NEXT:    call __floatunsidf
702; RV32I-NEXT:    sw a0, 0(s0)
703; RV32I-NEXT:    sw a1, 4(s0)
704; RV32I-NEXT:    mv a0, s1
705; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
706; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
707; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
708; RV32I-NEXT:    addi sp, sp, 16
709; RV32I-NEXT:    ret
710;
711; RV64I-LABEL: fcvt_d_wu_demanded_bits:
712; RV64I:       # %bb.0:
713; RV64I-NEXT:    addi sp, sp, -32
714; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
715; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
716; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
717; RV64I-NEXT:    mv s0, a1
718; RV64I-NEXT:    addiw s1, a0, 1
719; RV64I-NEXT:    mv a0, s1
720; RV64I-NEXT:    call __floatunsidf
721; RV64I-NEXT:    sd a0, 0(s0)
722; RV64I-NEXT:    mv a0, s1
723; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
724; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
725; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
726; RV64I-NEXT:    addi sp, sp, 32
727; RV64I-NEXT:    ret
728  %3 = add i32 %0, 1
729  %4 = uitofp i32 %3 to double
730  store double %4, ptr %1, align 8
731  ret i32 %3
732}
733
734define signext i16 @fcvt_w_s_i16(double %a) nounwind {
735; RV32IFD-LABEL: fcvt_w_s_i16:
736; RV32IFD:       # %bb.0:
737; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
738; RV32IFD-NEXT:    slli a0, a0, 16
739; RV32IFD-NEXT:    srai a0, a0, 16
740; RV32IFD-NEXT:    ret
741;
742; RV64IFD-LABEL: fcvt_w_s_i16:
743; RV64IFD:       # %bb.0:
744; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
745; RV64IFD-NEXT:    slli a0, a0, 48
746; RV64IFD-NEXT:    srai a0, a0, 48
747; RV64IFD-NEXT:    ret
748;
749; RV32I-LABEL: fcvt_w_s_i16:
750; RV32I:       # %bb.0:
751; RV32I-NEXT:    addi sp, sp, -16
752; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
753; RV32I-NEXT:    call __fixdfsi
754; RV32I-NEXT:    slli a0, a0, 16
755; RV32I-NEXT:    srai a0, a0, 16
756; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
757; RV32I-NEXT:    addi sp, sp, 16
758; RV32I-NEXT:    ret
759;
760; RV64I-LABEL: fcvt_w_s_i16:
761; RV64I:       # %bb.0:
762; RV64I-NEXT:    addi sp, sp, -16
763; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
764; RV64I-NEXT:    call __fixdfsi
765; RV64I-NEXT:    slli a0, a0, 48
766; RV64I-NEXT:    srai a0, a0, 48
767; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
768; RV64I-NEXT:    addi sp, sp, 16
769; RV64I-NEXT:    ret
770  %1 = fptosi double %a to i16
771  ret i16 %1
772}
773
774define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
775; RV32IFD-LABEL: fcvt_wu_s_i16:
776; RV32IFD:       # %bb.0:
777; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
778; RV32IFD-NEXT:    slli a0, a0, 16
779; RV32IFD-NEXT:    srli a0, a0, 16
780; RV32IFD-NEXT:    ret
781;
782; RV64IFD-LABEL: fcvt_wu_s_i16:
783; RV64IFD:       # %bb.0:
784; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
785; RV64IFD-NEXT:    slli a0, a0, 48
786; RV64IFD-NEXT:    srli a0, a0, 48
787; RV64IFD-NEXT:    ret
788;
789; RV32I-LABEL: fcvt_wu_s_i16:
790; RV32I:       # %bb.0:
791; RV32I-NEXT:    addi sp, sp, -16
792; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
793; RV32I-NEXT:    call __fixunsdfsi
794; RV32I-NEXT:    slli a0, a0, 16
795; RV32I-NEXT:    srli a0, a0, 16
796; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
797; RV32I-NEXT:    addi sp, sp, 16
798; RV32I-NEXT:    ret
799;
800; RV64I-LABEL: fcvt_wu_s_i16:
801; RV64I:       # %bb.0:
802; RV64I-NEXT:    addi sp, sp, -16
803; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
804; RV64I-NEXT:    call __fixunsdfsi
805; RV64I-NEXT:    slli a0, a0, 48
806; RV64I-NEXT:    srli a0, a0, 48
807; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
808; RV64I-NEXT:    addi sp, sp, 16
809; RV64I-NEXT:    ret
810  %1 = fptoui double %a to i16
811  ret i16 %1
812}
813
814define signext i8 @fcvt_w_s_i8(double %a) nounwind {
815; RV32IFD-LABEL: fcvt_w_s_i8:
816; RV32IFD:       # %bb.0:
817; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
818; RV32IFD-NEXT:    slli a0, a0, 24
819; RV32IFD-NEXT:    srai a0, a0, 24
820; RV32IFD-NEXT:    ret
821;
822; RV64IFD-LABEL: fcvt_w_s_i8:
823; RV64IFD:       # %bb.0:
824; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
825; RV64IFD-NEXT:    slli a0, a0, 56
826; RV64IFD-NEXT:    srai a0, a0, 56
827; RV64IFD-NEXT:    ret
828;
829; RV32I-LABEL: fcvt_w_s_i8:
830; RV32I:       # %bb.0:
831; RV32I-NEXT:    addi sp, sp, -16
832; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
833; RV32I-NEXT:    call __fixdfsi
834; RV32I-NEXT:    slli a0, a0, 24
835; RV32I-NEXT:    srai a0, a0, 24
836; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
837; RV32I-NEXT:    addi sp, sp, 16
838; RV32I-NEXT:    ret
839;
840; RV64I-LABEL: fcvt_w_s_i8:
841; RV64I:       # %bb.0:
842; RV64I-NEXT:    addi sp, sp, -16
843; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
844; RV64I-NEXT:    call __fixdfsi
845; RV64I-NEXT:    slli a0, a0, 56
846; RV64I-NEXT:    srai a0, a0, 56
847; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
848; RV64I-NEXT:    addi sp, sp, 16
849; RV64I-NEXT:    ret
850  %1 = fptosi double %a to i8
851  ret i8 %1
852}
853
854define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
855; CHECKIFD-LABEL: fcvt_wu_s_i8:
856; CHECKIFD:       # %bb.0:
857; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
858; CHECKIFD-NEXT:    andi a0, a0, 255
859; CHECKIFD-NEXT:    ret
860;
861; RV32I-LABEL: fcvt_wu_s_i8:
862; RV32I:       # %bb.0:
863; RV32I-NEXT:    addi sp, sp, -16
864; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
865; RV32I-NEXT:    call __fixunsdfsi
866; RV32I-NEXT:    andi a0, a0, 255
867; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
868; RV32I-NEXT:    addi sp, sp, 16
869; RV32I-NEXT:    ret
870;
871; RV64I-LABEL: fcvt_wu_s_i8:
872; RV64I:       # %bb.0:
873; RV64I-NEXT:    addi sp, sp, -16
874; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
875; RV64I-NEXT:    call __fixunsdfsi
876; RV64I-NEXT:    andi a0, a0, 255
877; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
878; RV64I-NEXT:    addi sp, sp, 16
879; RV64I-NEXT:    ret
880  %1 = fptoui double %a to i8
881  ret i8 %1
882}
883