xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/combine.mir (revision 0864501b97a70ce7d6f1741514fae08eef7c237e)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2# RUN: llc -run-pass=riscv-prelegalizer-combiner -mtriple riscv64 %s -o - | FileCheck %s --check-prefix=RV64
3
4---
5name:            nneg_zext
6body:             |
7  bb.0:
8
9    ; RV64-LABEL: name: nneg_zext
10    ; RV64: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
11    ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
12    ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s32)
13    ; RV64-NEXT: $x10 = COPY [[SEXT]](s64)
14    ; RV64-NEXT: PseudoRET implicit $x10
15    %0:_(s64) = COPY $x10
16    %2:_(s32) = G_TRUNC %0
17    %3:_(s64) = nneg G_ZEXT %2
18    $x10 = COPY %3(s64)
19    PseudoRET implicit $x10
20...
21