1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -stop-after=finalize-isel -verify-machineinstrs < %s | \ 4; RUN: FileCheck %s 5 6define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { 7 ; CHECK-LABEL: name: foo 8 ; CHECK: bb.0 (%ir-block.0): 9 ; CHECK-NEXT: liveins: $x3, $x4, $x5 10 ; CHECK-NEXT: {{ $}} 11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x5 12 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x4 13 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3 14 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32 15 ; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]] 16 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ]], %subreg.sub_64 17 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32 18 ; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]] 19 ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ1]], %subreg.sub_64 20 ; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]] 21 ; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got) 22 ; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool) 23 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 24 ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] 25 ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 26 ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] 27 ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8 28 ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] 29 ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2 30 %1 = insertelement <4 x i1> poison, i1 %c1, i64 0 31 %2 = insertelement <4 x i1> %1, i1 %c2, i64 1 32 %3 = insertelement <4 x i1> %2, i1 %c3, i64 3 33 %4 = shufflevector <4 x i1> %3, <4 x i1> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3> 34 ret <4 x i1> %4 35} 36