xref: /llvm-project/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll (revision 5403c59c608c08c8ecd4303763f08eb046eb5e4d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -ppc-vsr-nums-as-vr \
3; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
4; RUN:   | FileCheck %s
5
6; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -ppc-vsr-nums-as-vr \
7; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
8; RUN:   | FileCheck %s --check-prefix=CHECK-P8-BE
9
10; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector -ppc-vsr-nums-as-vr \
11; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
12; RUN:   | FileCheck --check-prefix=CHECK-P9-VECTOR %s
13
14; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
15; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
16; RUN:   --check-prefix=CHECK-P9 --implicit-check-not xxswapd
17
18define <2 x double> @testi0(ptr %p1, ptr %p2) {
19; CHECK-LABEL: testi0:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    lxvd2x vs0, 0, r3
22; CHECK-NEXT:    lfd f1, 0(r4)
23; CHECK-NEXT:    xxswapd vs0, vs0
24; CHECK-NEXT:    xxmrghd v2, vs0, vs1
25; CHECK-NEXT:    blr
26;
27; CHECK-P8-BE-LABEL: testi0:
28; CHECK-P8-BE:       # %bb.0:
29; CHECK-P8-BE-NEXT:    lxvd2x vs0, 0, r3
30; CHECK-P8-BE-NEXT:    lfd f1, 0(r4)
31; CHECK-P8-BE-NEXT:    xxpermdi v2, vs1, vs0, 1
32; CHECK-P8-BE-NEXT:    blr
33;
34; CHECK-P9-VECTOR-LABEL: testi0:
35; CHECK-P9-VECTOR:       # %bb.0:
36; CHECK-P9-VECTOR-NEXT:    lxvd2x vs0, 0, r3
37; CHECK-P9-VECTOR-NEXT:    lfd f1, 0(r4)
38; CHECK-P9-VECTOR-NEXT:    xxswapd vs0, vs0
39; CHECK-P9-VECTOR-NEXT:    xxmrghd v2, vs0, vs1
40; CHECK-P9-VECTOR-NEXT:    blr
41;
42; CHECK-P9-LABEL: testi0:
43; CHECK-P9:       # %bb.0:
44; CHECK-P9-NEXT:    lxv vs0, 0(r3)
45; CHECK-P9-NEXT:    lfd f1, 0(r4)
46; CHECK-P9-NEXT:    xxmrghd v2, vs0, vs1
47; CHECK-P9-NEXT:    blr
48  %v = load <2 x double>, ptr %p1
49  %s = load double, ptr %p2
50  %r = insertelement <2 x double> %v, double %s, i32 0
51  ret <2 x double> %r
52
53
54}
55
56define <2 x double> @testi1(ptr %p1, ptr %p2) {
57; CHECK-LABEL: testi1:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    lxvd2x vs0, 0, r3
60; CHECK-NEXT:    lfd f1, 0(r4)
61; CHECK-NEXT:    xxswapd vs0, vs0
62; CHECK-NEXT:    xxpermdi v2, vs1, vs0, 1
63; CHECK-NEXT:    blr
64;
65; CHECK-P8-BE-LABEL: testi1:
66; CHECK-P8-BE:       # %bb.0:
67; CHECK-P8-BE-NEXT:    lxvd2x vs0, 0, r3
68; CHECK-P8-BE-NEXT:    lfd f1, 0(r4)
69; CHECK-P8-BE-NEXT:    xxmrghd v2, vs0, vs1
70; CHECK-P8-BE-NEXT:    blr
71;
72; CHECK-P9-VECTOR-LABEL: testi1:
73; CHECK-P9-VECTOR:       # %bb.0:
74; CHECK-P9-VECTOR-NEXT:    lxvd2x vs0, 0, r3
75; CHECK-P9-VECTOR-NEXT:    lfd f1, 0(r4)
76; CHECK-P9-VECTOR-NEXT:    xxswapd vs0, vs0
77; CHECK-P9-VECTOR-NEXT:    xxpermdi v2, vs1, vs0, 1
78; CHECK-P9-VECTOR-NEXT:    blr
79;
80; CHECK-P9-LABEL: testi1:
81; CHECK-P9:       # %bb.0:
82; CHECK-P9-NEXT:    lxv vs0, 0(r3)
83; CHECK-P9-NEXT:    lfd f1, 0(r4)
84; CHECK-P9-NEXT:    xxpermdi v2, vs1, vs0, 1
85; CHECK-P9-NEXT:    blr
86  %v = load <2 x double>, ptr %p1
87  %s = load double, ptr %p2
88  %r = insertelement <2 x double> %v, double %s, i32 1
89  ret <2 x double> %r
90
91
92}
93
94define double @teste0(ptr %p1) {
95; CHECK-LABEL: teste0:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    lfd f1, 0(r3)
98; CHECK-NEXT:    blr
99;
100; CHECK-P8-BE-LABEL: teste0:
101; CHECK-P8-BE:       # %bb.0:
102; CHECK-P8-BE-NEXT:    lfd f1, 0(r3)
103; CHECK-P8-BE-NEXT:    blr
104;
105; CHECK-P9-VECTOR-LABEL: teste0:
106; CHECK-P9-VECTOR:       # %bb.0:
107; CHECK-P9-VECTOR-NEXT:    lfd f1, 0(r3)
108; CHECK-P9-VECTOR-NEXT:    blr
109;
110; CHECK-P9-LABEL: teste0:
111; CHECK-P9:       # %bb.0:
112; CHECK-P9-NEXT:    lfd f1, 0(r3)
113; CHECK-P9-NEXT:    blr
114  %v = load <2 x double>, ptr %p1
115  %r = extractelement <2 x double> %v, i32 0
116  ret double %r
117
118
119}
120
121define double @teste1(ptr %p1) {
122; CHECK-LABEL: teste1:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    lfd f1, 8(r3)
125; CHECK-NEXT:    blr
126;
127; CHECK-P8-BE-LABEL: teste1:
128; CHECK-P8-BE:       # %bb.0:
129; CHECK-P8-BE-NEXT:    lfd f1, 8(r3)
130; CHECK-P8-BE-NEXT:    blr
131;
132; CHECK-P9-VECTOR-LABEL: teste1:
133; CHECK-P9-VECTOR:       # %bb.0:
134; CHECK-P9-VECTOR-NEXT:    lfd f1, 8(r3)
135; CHECK-P9-VECTOR-NEXT:    blr
136;
137; CHECK-P9-LABEL: teste1:
138; CHECK-P9:       # %bb.0:
139; CHECK-P9-NEXT:    lfd f1, 8(r3)
140; CHECK-P9-NEXT:    blr
141  %v = load <2 x double>, ptr %p1
142  %r = extractelement <2 x double> %v, i32 1
143  ret double %r
144
145
146}
147