1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \ 3; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 5; RUN: --check-prefixes=CHECK,CHECK-P9UP 6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ 7; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ 8; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 9; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN 10; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ 11; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ 12; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 13; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN 14; RUN: llc -verify-machineinstrs -mcpu=pwr9 \ 15; RUN: -mtriple=powerpc64-unknown-linux-gnu \ 16; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 17; RUN: --check-prefixes=CHECK,CHECK-P9UP 18; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ 19; RUN: -mtriple=powerpc64-unknown-linux-gnu \ 20; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 21; RUN: --check-prefixes=CHECK,CHECK-INTRIN 22; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ 23; RUN: -mtriple=powerpc64-unknown-linux-gnu \ 24; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 25; RUN: --check-prefixes=CHECK,CHECK-INTRIN 26; RUN: llc -verify-machineinstrs -mcpu=pwr10 \ 27; RUN: -mtriple=powerpc64-unknown-linux-gnu \ 28; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 29; RUN: --check-prefixes=CHECK,CHECK-P9UP 30; RUN: llc -verify-machineinstrs -mcpu=pwr10 \ 31; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ 32; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ 33; RUN: --check-prefixes=CHECK,CHECK-P9UP 34 35; Function Attrs: nounwind readnone 36define <4 x i32> @test1(ptr %a) { 37; CHECK-LABEL: test1: 38; CHECK: # %bb.0: # %entry 39; CHECK-NEXT: lxvw4x v2, 0, r3 40; CHECK-NEXT: blr 41 entry: 42 %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %a) 43 ret <4 x i32> %0 44} 45; Function Attrs: nounwind readnone 46declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr) 47 48; Function Attrs: nounwind readnone 49define <2 x double> @test2(ptr %a) { 50; CHECK-LABEL: test2: 51; CHECK: # %bb.0: # %entry 52; CHECK-NEXT: lxvd2x v2, 0, r3 53; CHECK-NEXT: blr 54 entry: 55 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %a) 56 ret <2 x double> %0 57} 58; Function Attrs: nounwind readnone 59declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr) 60 61; Function Attrs: nounwind readnone 62define void @test3(<4 x i32> %a, ptr %b) { 63; CHECK-LABEL: test3: 64; CHECK: # %bb.0: # %entry 65; CHECK-NEXT: stxvw4x v2, 0, r5 66; CHECK-NEXT: blr 67 entry: 68 tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, ptr %b) 69 ret void 70} 71; Function Attrs: nounwind readnone 72declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, ptr) 73 74; Function Attrs: nounwind readnone 75define void @test4(<2 x double> %a, ptr %b) { 76; CHECK-LABEL: test4: 77; CHECK: # %bb.0: # %entry 78; CHECK-NEXT: stxvd2x v2, 0, r5 79; CHECK-NEXT: blr 80 entry: 81 tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, ptr %b) 82 ret void 83} 84; Function Attrs: nounwind readnone 85declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, ptr) 86 87define i32 @test_vec_test_swdiv(<2 x double> %a, <2 x double> %b) { 88; CHECK-LABEL: test_vec_test_swdiv: 89; CHECK: # %bb.0: # %entry 90; CHECK-NEXT: xvtdivdp cr0, v2, v3 91; CHECK-NEXT: mfocrf r3, 128 92; CHECK-NEXT: srwi r3, r3, 28 93; CHECK-NEXT: blr 94 entry: 95 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 96 ret i32 %0 97} 98declare i32 @llvm.ppc.vsx.xvtdivdp(<2 x double>, <2 x double>) 99 100define i32 @test_vec_test_swdivs(<4 x float> %a, <4 x float> %b) { 101; CHECK-LABEL: test_vec_test_swdivs: 102; CHECK: # %bb.0: # %entry 103; CHECK-NEXT: xvtdivsp cr0, v2, v3 104; CHECK-NEXT: mfocrf r3, 128 105; CHECK-NEXT: srwi r3, r3, 28 106; CHECK-NEXT: blr 107 entry: 108 %0 = tail call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %a, <4 x float> %b) 109 ret i32 %0 110} 111declare i32 @llvm.ppc.vsx.xvtdivsp(<4 x float>, <4 x float>) 112 113define i32 @test_vec_test_swsqrt(<2 x double> %a) { 114; CHECK-LABEL: test_vec_test_swsqrt: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: xvtsqrtdp cr0, v2 117; CHECK-NEXT: mfocrf r3, 128 118; CHECK-NEXT: srwi r3, r3, 28 119; CHECK-NEXT: blr 120 entry: 121 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %a) 122 ret i32 %0 123} 124declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>) 125 126define i32 @test_vec_test_swsqrts(<4 x float> %a) { 127; CHECK-LABEL: test_vec_test_swsqrts: 128; CHECK: # %bb.0: # %entry 129; CHECK-NEXT: xvtsqrtsp cr0, v2 130; CHECK-NEXT: mfocrf r3, 128 131; CHECK-NEXT: srwi r3, r3, 28 132; CHECK-NEXT: blr 133 entry: 134 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %a) 135 ret i32 %0 136} 137declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>) 138 139define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) { 140; CHECK-LABEL: xvtdivdp_andi: 141; CHECK: # %bb.0: # %entry 142; CHECK-NEXT: xvtdivdp cr0, v2, v3 143; CHECK-NEXT: li r4, 222 144; CHECK-NEXT: mfocrf r3, 128 145; CHECK-NEXT: srwi r3, r3, 28 146; CHECK-NEXT: andi. r3, r3, 2 147; CHECK-NEXT: li r3, 22 148; CHECK-NEXT: iseleq r3, r4, r3 149; CHECK-NEXT: blr 150 entry: 151 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 152 %1 = and i32 %0, 2 153 %cmp.not = icmp eq i32 %1, 0 154 %retval.0 = select i1 %cmp.not, i32 222, i32 22 155 ret i32 %retval.0 156} 157 158define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) { 159; CHECK-LABEL: xvtdivdp_shift: 160; CHECK: # %bb.0: # %entry 161; CHECK-NEXT: xvtdivdp cr0, v2, v3 162; CHECK-NEXT: mfocrf r3, 128 163; CHECK-NEXT: srwi r3, r3, 28 164; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31 165; CHECK-NEXT: blr 166entry: 167 %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) 168 %1 = lshr i32 %0, 4 169 %.lobit = and i32 %1, 1 170 ret i32 %.lobit 171} 172 173; Function Attrs: nounwind readnone 174define <2 x double> @test_lxvd2x(ptr %a) { 175; CHECK-P9UP-LABEL: test_lxvd2x: 176; CHECK-P9UP: # %bb.0: # %entry 177; CHECK-P9UP-NEXT: lxv v2, 0(r3) 178; CHECK-P9UP-NEXT: blr 179; 180; CHECK-NOINTRIN-LABEL: test_lxvd2x: 181; CHECK-NOINTRIN: # %bb.0: # %entry 182; CHECK-NOINTRIN-NEXT: lxvd2x vs0, 0, r3 183; CHECK-NOINTRIN-NEXT: xxswapd v2, vs0 184; CHECK-NOINTRIN-NEXT: blr 185; 186; CHECK-INTRIN-LABEL: test_lxvd2x: 187; CHECK-INTRIN: # %bb.0: # %entry 188; CHECK-INTRIN-NEXT: lxvd2x v2, 0, r3 189; CHECK-INTRIN-NEXT: blr 190entry: 191 %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %a) 192 ret <2 x double> %0 193} 194; Function Attrs: nounwind readnone 195declare <2 x double> @llvm.ppc.vsx.lxvd2x(ptr) 196 197; Function Attrs: nounwind readnone 198define void @test_stxvd2x(<2 x double> %a, ptr %b) { 199; CHECK-P9UP-LABEL: test_stxvd2x: 200; CHECK-P9UP: # %bb.0: # %entry 201; CHECK-P9UP-NEXT: stxv v2, 0(r5) 202; CHECK-P9UP-NEXT: blr 203; 204; CHECK-NOINTRIN-LABEL: test_stxvd2x: 205; CHECK-NOINTRIN: # %bb.0: # %entry 206; CHECK-NOINTRIN-NEXT: xxswapd vs0, v2 207; CHECK-NOINTRIN-NEXT: stxvd2x vs0, 0, r5 208; CHECK-NOINTRIN-NEXT: blr 209; 210; CHECK-INTRIN-LABEL: test_stxvd2x: 211; CHECK-INTRIN: # %bb.0: # %entry 212; CHECK-INTRIN-NEXT: stxvd2x v2, 0, r5 213; CHECK-INTRIN-NEXT: blr 214entry: 215 tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, ptr %b) 216 ret void 217} 218; Function Attrs: nounwind readnone 219declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, ptr) 220