xref: /llvm-project/llvm/test/CodeGen/PowerPC/vsx.ll (revision 8b6e9de3dd114db28fde892c67960a87d9870637) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
3; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
4; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
5; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
6; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
7; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
8; RUN:     -check-prefix=CHECK-REG %s
9; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
10; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \
11; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
12; RUN:     -check-prefix=CHECK-FISL %s
13; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
14; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
15; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
16; RUN:     -check-prefix=CHECK-LE %s
17
18define double @test1(double %a, double %b) {
19; CHECK-LABEL: test1:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xsmuldp f1, f1, f2
22; CHECK-NEXT:    blr
23;
24; CHECK-REG-LABEL: test1:
25; CHECK-REG:       # %bb.0: # %entry
26; CHECK-REG-NEXT:    xsmuldp f1, f1, f2
27; CHECK-REG-NEXT:    blr
28;
29; CHECK-FISL-LABEL: test1:
30; CHECK-FISL:       # %bb.0: # %entry
31; CHECK-FISL-NEXT:    xsmuldp f1, f1, f2
32; CHECK-FISL-NEXT:    blr
33;
34; CHECK-LE-LABEL: test1:
35; CHECK-LE:       # %bb.0: # %entry
36; CHECK-LE-NEXT:    xsmuldp f1, f1, f2
37; CHECK-LE-NEXT:    blr
38entry:
39  %v = fmul double %a, %b
40  ret double %v
41
42
43}
44
45define double @test2(double %a, double %b) {
46; CHECK-LABEL: test2:
47; CHECK:       # %bb.0: # %entry
48; CHECK-NEXT:    xsdivdp f1, f1, f2
49; CHECK-NEXT:    blr
50;
51; CHECK-REG-LABEL: test2:
52; CHECK-REG:       # %bb.0: # %entry
53; CHECK-REG-NEXT:    xsdivdp f1, f1, f2
54; CHECK-REG-NEXT:    blr
55;
56; CHECK-FISL-LABEL: test2:
57; CHECK-FISL:       # %bb.0: # %entry
58; CHECK-FISL-NEXT:    xsdivdp f1, f1, f2
59; CHECK-FISL-NEXT:    blr
60;
61; CHECK-LE-LABEL: test2:
62; CHECK-LE:       # %bb.0: # %entry
63; CHECK-LE-NEXT:    xsdivdp f1, f1, f2
64; CHECK-LE-NEXT:    blr
65entry:
66  %v = fdiv double %a, %b
67  ret double %v
68
69
70}
71
72define double @test3(double %a, double %b) {
73; CHECK-LABEL: test3:
74; CHECK:       # %bb.0: # %entry
75; CHECK-NEXT:    xsadddp f1, f1, f2
76; CHECK-NEXT:    blr
77;
78; CHECK-REG-LABEL: test3:
79; CHECK-REG:       # %bb.0: # %entry
80; CHECK-REG-NEXT:    xsadddp f1, f1, f2
81; CHECK-REG-NEXT:    blr
82;
83; CHECK-FISL-LABEL: test3:
84; CHECK-FISL:       # %bb.0: # %entry
85; CHECK-FISL-NEXT:    xsadddp f1, f1, f2
86; CHECK-FISL-NEXT:    blr
87;
88; CHECK-LE-LABEL: test3:
89; CHECK-LE:       # %bb.0: # %entry
90; CHECK-LE-NEXT:    xsadddp f1, f1, f2
91; CHECK-LE-NEXT:    blr
92entry:
93  %v = fadd double %a, %b
94  ret double %v
95
96
97}
98
99define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
100; CHECK-LABEL: test4:
101; CHECK:       # %bb.0: # %entry
102; CHECK-NEXT:    xvadddp v2, v2, v3
103; CHECK-NEXT:    blr
104;
105; CHECK-REG-LABEL: test4:
106; CHECK-REG:       # %bb.0: # %entry
107; CHECK-REG-NEXT:    xvadddp v2, v2, v3
108; CHECK-REG-NEXT:    blr
109;
110; CHECK-FISL-LABEL: test4:
111; CHECK-FISL:       # %bb.0: # %entry
112; CHECK-FISL-NEXT:    xvadddp v2, v2, v3
113; CHECK-FISL-NEXT:    blr
114;
115; CHECK-LE-LABEL: test4:
116; CHECK-LE:       # %bb.0: # %entry
117; CHECK-LE-NEXT:    xvadddp v2, v2, v3
118; CHECK-LE-NEXT:    blr
119entry:
120  %v = fadd <2 x double> %a, %b
121  ret <2 x double> %v
122
123
124}
125
126define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
127; CHECK-LABEL: test5:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    xxlxor v2, v2, v3
130; CHECK-NEXT:    blr
131;
132; CHECK-REG-LABEL: test5:
133; CHECK-REG:       # %bb.0: # %entry
134; CHECK-REG-NEXT:    xxlxor v2, v2, v3
135; CHECK-REG-NEXT:    blr
136;
137; CHECK-FISL-LABEL: test5:
138; CHECK-FISL:       # %bb.0: # %entry
139; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
140; CHECK-FISL-NEXT:    blr
141;
142; CHECK-LE-LABEL: test5:
143; CHECK-LE:       # %bb.0: # %entry
144; CHECK-LE-NEXT:    xxlxor v2, v2, v3
145; CHECK-LE-NEXT:    blr
146entry:
147  %v = xor <4 x i32> %a, %b
148  ret <4 x i32> %v
149
150
151
152}
153
154define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
155; CHECK-LABEL: test6:
156; CHECK:       # %bb.0: # %entry
157; CHECK-NEXT:    xxlxor v2, v2, v3
158; CHECK-NEXT:    blr
159;
160; CHECK-REG-LABEL: test6:
161; CHECK-REG:       # %bb.0: # %entry
162; CHECK-REG-NEXT:    xxlxor v2, v2, v3
163; CHECK-REG-NEXT:    blr
164;
165; CHECK-FISL-LABEL: test6:
166; CHECK-FISL:       # %bb.0: # %entry
167; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
168; CHECK-FISL-NEXT:    blr
169;
170; CHECK-LE-LABEL: test6:
171; CHECK-LE:       # %bb.0: # %entry
172; CHECK-LE-NEXT:    xxlxor v2, v2, v3
173; CHECK-LE-NEXT:    blr
174entry:
175  %v = xor <8 x i16> %a, %b
176  ret <8 x i16> %v
177
178
179
180}
181
182define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
183; CHECK-LABEL: test7:
184; CHECK:       # %bb.0: # %entry
185; CHECK-NEXT:    xxlxor v2, v2, v3
186; CHECK-NEXT:    blr
187;
188; CHECK-REG-LABEL: test7:
189; CHECK-REG:       # %bb.0: # %entry
190; CHECK-REG-NEXT:    xxlxor v2, v2, v3
191; CHECK-REG-NEXT:    blr
192;
193; CHECK-FISL-LABEL: test7:
194; CHECK-FISL:       # %bb.0: # %entry
195; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
196; CHECK-FISL-NEXT:    blr
197;
198; CHECK-LE-LABEL: test7:
199; CHECK-LE:       # %bb.0: # %entry
200; CHECK-LE-NEXT:    xxlxor v2, v2, v3
201; CHECK-LE-NEXT:    blr
202entry:
203  %v = xor <16 x i8> %a, %b
204  ret <16 x i8> %v
205
206
207
208}
209
210define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
211; CHECK-LABEL: test8:
212; CHECK:       # %bb.0: # %entry
213; CHECK-NEXT:    xxlor v2, v2, v3
214; CHECK-NEXT:    blr
215;
216; CHECK-REG-LABEL: test8:
217; CHECK-REG:       # %bb.0: # %entry
218; CHECK-REG-NEXT:    xxlor v2, v2, v3
219; CHECK-REG-NEXT:    blr
220;
221; CHECK-FISL-LABEL: test8:
222; CHECK-FISL:       # %bb.0: # %entry
223; CHECK-FISL-NEXT:    xxlor v2, v2, v3
224; CHECK-FISL-NEXT:    blr
225;
226; CHECK-LE-LABEL: test8:
227; CHECK-LE:       # %bb.0: # %entry
228; CHECK-LE-NEXT:    xxlor v2, v2, v3
229; CHECK-LE-NEXT:    blr
230entry:
231  %v = or <4 x i32> %a, %b
232  ret <4 x i32> %v
233
234
235
236}
237
238define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
239; CHECK-LABEL: test9:
240; CHECK:       # %bb.0: # %entry
241; CHECK-NEXT:    xxlor v2, v2, v3
242; CHECK-NEXT:    blr
243;
244; CHECK-REG-LABEL: test9:
245; CHECK-REG:       # %bb.0: # %entry
246; CHECK-REG-NEXT:    xxlor v2, v2, v3
247; CHECK-REG-NEXT:    blr
248;
249; CHECK-FISL-LABEL: test9:
250; CHECK-FISL:       # %bb.0: # %entry
251; CHECK-FISL-NEXT:    xxlor v2, v2, v3
252; CHECK-FISL-NEXT:    blr
253;
254; CHECK-LE-LABEL: test9:
255; CHECK-LE:       # %bb.0: # %entry
256; CHECK-LE-NEXT:    xxlor v2, v2, v3
257; CHECK-LE-NEXT:    blr
258entry:
259  %v = or <8 x i16> %a, %b
260  ret <8 x i16> %v
261
262
263
264}
265
266define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
267; CHECK-LABEL: test10:
268; CHECK:       # %bb.0: # %entry
269; CHECK-NEXT:    xxlor v2, v2, v3
270; CHECK-NEXT:    blr
271;
272; CHECK-REG-LABEL: test10:
273; CHECK-REG:       # %bb.0: # %entry
274; CHECK-REG-NEXT:    xxlor v2, v2, v3
275; CHECK-REG-NEXT:    blr
276;
277; CHECK-FISL-LABEL: test10:
278; CHECK-FISL:       # %bb.0: # %entry
279; CHECK-FISL-NEXT:    xxlor v2, v2, v3
280; CHECK-FISL-NEXT:    blr
281;
282; CHECK-LE-LABEL: test10:
283; CHECK-LE:       # %bb.0: # %entry
284; CHECK-LE-NEXT:    xxlor v2, v2, v3
285; CHECK-LE-NEXT:    blr
286entry:
287  %v = or <16 x i8> %a, %b
288  ret <16 x i8> %v
289
290
291
292}
293
294define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
295; CHECK-LABEL: test11:
296; CHECK:       # %bb.0: # %entry
297; CHECK-NEXT:    xxland v2, v2, v3
298; CHECK-NEXT:    blr
299;
300; CHECK-REG-LABEL: test11:
301; CHECK-REG:       # %bb.0: # %entry
302; CHECK-REG-NEXT:    xxland v2, v2, v3
303; CHECK-REG-NEXT:    blr
304;
305; CHECK-FISL-LABEL: test11:
306; CHECK-FISL:       # %bb.0: # %entry
307; CHECK-FISL-NEXT:    xxland v2, v2, v3
308; CHECK-FISL-NEXT:    blr
309;
310; CHECK-LE-LABEL: test11:
311; CHECK-LE:       # %bb.0: # %entry
312; CHECK-LE-NEXT:    xxland v2, v2, v3
313; CHECK-LE-NEXT:    blr
314entry:
315  %v = and <4 x i32> %a, %b
316  ret <4 x i32> %v
317
318
319
320}
321
322define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
323; CHECK-LABEL: test12:
324; CHECK:       # %bb.0: # %entry
325; CHECK-NEXT:    xxland v2, v2, v3
326; CHECK-NEXT:    blr
327;
328; CHECK-REG-LABEL: test12:
329; CHECK-REG:       # %bb.0: # %entry
330; CHECK-REG-NEXT:    xxland v2, v2, v3
331; CHECK-REG-NEXT:    blr
332;
333; CHECK-FISL-LABEL: test12:
334; CHECK-FISL:       # %bb.0: # %entry
335; CHECK-FISL-NEXT:    xxland v2, v2, v3
336; CHECK-FISL-NEXT:    blr
337;
338; CHECK-LE-LABEL: test12:
339; CHECK-LE:       # %bb.0: # %entry
340; CHECK-LE-NEXT:    xxland v2, v2, v3
341; CHECK-LE-NEXT:    blr
342entry:
343  %v = and <8 x i16> %a, %b
344  ret <8 x i16> %v
345
346
347
348}
349
350define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
351; CHECK-LABEL: test13:
352; CHECK:       # %bb.0: # %entry
353; CHECK-NEXT:    xxland v2, v2, v3
354; CHECK-NEXT:    blr
355;
356; CHECK-REG-LABEL: test13:
357; CHECK-REG:       # %bb.0: # %entry
358; CHECK-REG-NEXT:    xxland v2, v2, v3
359; CHECK-REG-NEXT:    blr
360;
361; CHECK-FISL-LABEL: test13:
362; CHECK-FISL:       # %bb.0: # %entry
363; CHECK-FISL-NEXT:    xxland v2, v2, v3
364; CHECK-FISL-NEXT:    blr
365;
366; CHECK-LE-LABEL: test13:
367; CHECK-LE:       # %bb.0: # %entry
368; CHECK-LE-NEXT:    xxland v2, v2, v3
369; CHECK-LE-NEXT:    blr
370entry:
371  %v = and <16 x i8> %a, %b
372  ret <16 x i8> %v
373
374
375
376}
377
378define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
379; CHECK-LABEL: test14:
380; CHECK:       # %bb.0: # %entry
381; CHECK-NEXT:    xxlnor v2, v2, v3
382; CHECK-NEXT:    blr
383;
384; CHECK-REG-LABEL: test14:
385; CHECK-REG:       # %bb.0: # %entry
386; CHECK-REG-NEXT:    xxlnor v2, v2, v3
387; CHECK-REG-NEXT:    blr
388;
389; CHECK-FISL-LABEL: test14:
390; CHECK-FISL:       # %bb.0: # %entry
391; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
392; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
393; CHECK-FISL-NEXT:    blr
394;
395; CHECK-LE-LABEL: test14:
396; CHECK-LE:       # %bb.0: # %entry
397; CHECK-LE-NEXT:    xxlnor v2, v2, v3
398; CHECK-LE-NEXT:    blr
399entry:
400  %v = or <4 x i32> %a, %b
401  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
402  ret <4 x i32> %w
403
404
405
406}
407
408define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
409; CHECK-LABEL: test15:
410; CHECK:       # %bb.0: # %entry
411; CHECK-NEXT:    xxlnor v2, v2, v3
412; CHECK-NEXT:    blr
413;
414; CHECK-REG-LABEL: test15:
415; CHECK-REG:       # %bb.0: # %entry
416; CHECK-REG-NEXT:    xxlnor v2, v2, v3
417; CHECK-REG-NEXT:    blr
418;
419; CHECK-FISL-LABEL: test15:
420; CHECK-FISL:       # %bb.0: # %entry
421; CHECK-FISL-NEXT:    xxlor v4, v2, v3
422; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
423; CHECK-FISL-NEXT:    blr
424;
425; CHECK-LE-LABEL: test15:
426; CHECK-LE:       # %bb.0: # %entry
427; CHECK-LE-NEXT:    xxlnor v2, v2, v3
428; CHECK-LE-NEXT:    blr
429entry:
430  %v = or <8 x i16> %a, %b
431  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
432  ret <8 x i16> %w
433
434
435
436}
437
438define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
439; CHECK-LABEL: test16:
440; CHECK:       # %bb.0: # %entry
441; CHECK-NEXT:    xxlnor v2, v2, v3
442; CHECK-NEXT:    blr
443;
444; CHECK-REG-LABEL: test16:
445; CHECK-REG:       # %bb.0: # %entry
446; CHECK-REG-NEXT:    xxlnor v2, v2, v3
447; CHECK-REG-NEXT:    blr
448;
449; CHECK-FISL-LABEL: test16:
450; CHECK-FISL:       # %bb.0: # %entry
451; CHECK-FISL-NEXT:    xxlor v4, v2, v3
452; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
453; CHECK-FISL-NEXT:    blr
454;
455; CHECK-LE-LABEL: test16:
456; CHECK-LE:       # %bb.0: # %entry
457; CHECK-LE-NEXT:    xxlnor v2, v2, v3
458; CHECK-LE-NEXT:    blr
459entry:
460  %v = or <16 x i8> %a, %b
461  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
462  ret <16 x i8> %w
463
464
465
466}
467
468define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
469; CHECK-LABEL: test17:
470; CHECK:       # %bb.0: # %entry
471; CHECK-NEXT:    xxlandc v2, v2, v3
472; CHECK-NEXT:    blr
473;
474; CHECK-REG-LABEL: test17:
475; CHECK-REG:       # %bb.0: # %entry
476; CHECK-REG-NEXT:    xxlandc v2, v2, v3
477; CHECK-REG-NEXT:    blr
478;
479; CHECK-FISL-LABEL: test17:
480; CHECK-FISL:       # %bb.0: # %entry
481; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3
482; CHECK-FISL-NEXT:    xxland v2, v2, vs0
483; CHECK-FISL-NEXT:    blr
484;
485; CHECK-LE-LABEL: test17:
486; CHECK-LE:       # %bb.0: # %entry
487; CHECK-LE-NEXT:    xxlandc v2, v2, v3
488; CHECK-LE-NEXT:    blr
489entry:
490  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
491  %v = and <4 x i32> %a, %w
492  ret <4 x i32> %v
493
494
495
496}
497
498define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
499; CHECK-LABEL: test18:
500; CHECK:       # %bb.0: # %entry
501; CHECK-NEXT:    xxlandc v2, v2, v3
502; CHECK-NEXT:    blr
503;
504; CHECK-REG-LABEL: test18:
505; CHECK-REG:       # %bb.0: # %entry
506; CHECK-REG-NEXT:    xxlandc v2, v2, v3
507; CHECK-REG-NEXT:    blr
508;
509; CHECK-FISL-LABEL: test18:
510; CHECK-FISL:       # %bb.0: # %entry
511; CHECK-FISL-NEXT:    xxlnor v4, v3, v3
512; CHECK-FISL-NEXT:    xxlandc v2, v2, v3
513; CHECK-FISL-NEXT:    blr
514;
515; CHECK-LE-LABEL: test18:
516; CHECK-LE:       # %bb.0: # %entry
517; CHECK-LE-NEXT:    xxlandc v2, v2, v3
518; CHECK-LE-NEXT:    blr
519entry:
520  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
521  %v = and <8 x i16> %a, %w
522  ret <8 x i16> %v
523
524
525
526}
527
528define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
529; CHECK-LABEL: test19:
530; CHECK:       # %bb.0: # %entry
531; CHECK-NEXT:    xxlandc v2, v2, v3
532; CHECK-NEXT:    blr
533;
534; CHECK-REG-LABEL: test19:
535; CHECK-REG:       # %bb.0: # %entry
536; CHECK-REG-NEXT:    xxlandc v2, v2, v3
537; CHECK-REG-NEXT:    blr
538;
539; CHECK-FISL-LABEL: test19:
540; CHECK-FISL:       # %bb.0: # %entry
541; CHECK-FISL-NEXT:    xxlnor v4, v3, v3
542; CHECK-FISL-NEXT:    xxlandc v2, v2, v3
543; CHECK-FISL-NEXT:    blr
544;
545; CHECK-LE-LABEL: test19:
546; CHECK-LE:       # %bb.0: # %entry
547; CHECK-LE-NEXT:    xxlandc v2, v2, v3
548; CHECK-LE-NEXT:    blr
549entry:
550  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
551  %v = and <16 x i8> %a, %w
552  ret <16 x i8> %v
553
554
555
556}
557
558define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
559; CHECK-LABEL: test20:
560; CHECK:       # %bb.0: # %entry
561; CHECK-NEXT:    vcmpequw v4, v4, v5
562; CHECK-NEXT:    xxsel v2, v3, v2, v4
563; CHECK-NEXT:    blr
564;
565; CHECK-REG-LABEL: test20:
566; CHECK-REG:       # %bb.0: # %entry
567; CHECK-REG-NEXT:    vcmpequw v4, v4, v5
568; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
569; CHECK-REG-NEXT:    blr
570;
571; CHECK-FISL-LABEL: test20:
572; CHECK-FISL:       # %bb.0: # %entry
573; CHECK-FISL-NEXT:    vcmpequw v4, v4, v5
574; CHECK-FISL-NEXT:    xxsel v2, v3, v2, v4
575; CHECK-FISL-NEXT:    blr
576;
577; CHECK-LE-LABEL: test20:
578; CHECK-LE:       # %bb.0: # %entry
579; CHECK-LE-NEXT:    vcmpequw v4, v4, v5
580; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
581; CHECK-LE-NEXT:    blr
582entry:
583  %m = icmp eq <4 x i32> %c, %d
584  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
585  ret <4 x i32> %v
586
587
588
589}
590
591define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
592; CHECK-LABEL: test21:
593; CHECK:       # %bb.0: # %entry
594; CHECK-NEXT:    xvcmpeqsp vs0, v4, v5
595; CHECK-NEXT:    xxsel v2, v3, v2, vs0
596; CHECK-NEXT:    blr
597;
598; CHECK-REG-LABEL: test21:
599; CHECK-REG:       # %bb.0: # %entry
600; CHECK-REG-NEXT:    xvcmpeqsp vs0, v4, v5
601; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
602; CHECK-REG-NEXT:    blr
603;
604; CHECK-FISL-LABEL: test21:
605; CHECK-FISL:       # %bb.0: # %entry
606; CHECK-FISL-NEXT:    xvcmpeqsp vs0, v4, v5
607; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
608; CHECK-FISL-NEXT:    blr
609;
610; CHECK-LE-LABEL: test21:
611; CHECK-LE:       # %bb.0: # %entry
612; CHECK-LE-NEXT:    xvcmpeqsp vs0, v4, v5
613; CHECK-LE-NEXT:    xxsel v2, v3, v2, vs0
614; CHECK-LE-NEXT:    blr
615entry:
616  %m = fcmp oeq <4 x float> %c, %d
617  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
618  ret <4 x float> %v
619
620
621
622}
623
624define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
625; CHECK-LABEL: test22:
626; CHECK:       # %bb.0: # %entry
627; CHECK-NEXT:    xvcmpgtsp vs0, v5, v4
628; CHECK-NEXT:    xvcmpgtsp vs1, v4, v5
629; CHECK-NEXT:    xxlor vs0, vs1, vs0
630; CHECK-NEXT:    xxsel v2, v2, v3, vs0
631; CHECK-NEXT:    blr
632;
633; CHECK-REG-LABEL: test22:
634; CHECK-REG:       # %bb.0: # %entry
635; CHECK-REG-NEXT:    xvcmpgtsp vs0, v5, v4
636; CHECK-REG-NEXT:    xvcmpgtsp vs1, v4, v5
637; CHECK-REG-NEXT:    xxlor vs0, vs1, vs0
638; CHECK-REG-NEXT:    xxsel v2, v2, v3, vs0
639; CHECK-REG-NEXT:    blr
640;
641; CHECK-FISL-LABEL: test22:
642; CHECK-FISL:       # %bb.0: # %entry
643; CHECK-FISL-NEXT:    xvcmpgtsp vs1, v5, v4
644; CHECK-FISL-NEXT:    xvcmpgtsp vs0, v4, v5
645; CHECK-FISL-NEXT:    xxlor vs0, vs0, vs1
646; CHECK-FISL-NEXT:    xxsel v2, v2, v3, vs0
647; CHECK-FISL-NEXT:    blr
648;
649; CHECK-LE-LABEL: test22:
650; CHECK-LE:       # %bb.0: # %entry
651; CHECK-LE-NEXT:    xvcmpgtsp vs0, v5, v4
652; CHECK-LE-NEXT:    xvcmpgtsp vs1, v4, v5
653; CHECK-LE-NEXT:    xxlor vs0, vs1, vs0
654; CHECK-LE-NEXT:    xxsel v2, v2, v3, vs0
655; CHECK-LE-NEXT:    blr
656entry:
657  %m = fcmp ueq <4 x float> %c, %d
658  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
659  ret <4 x float> %v
660
661
662
663}
664
665define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
666; CHECK-LABEL: test23:
667; CHECK:       # %bb.0: # %entry
668; CHECK-NEXT:    vcmpequh v4, v4, v5
669; CHECK-NEXT:    xxsel v2, v3, v2, v4
670; CHECK-NEXT:    blr
671;
672; CHECK-REG-LABEL: test23:
673; CHECK-REG:       # %bb.0: # %entry
674; CHECK-REG-NEXT:    vcmpequh v4, v4, v5
675; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
676; CHECK-REG-NEXT:    blr
677;
678; CHECK-FISL-LABEL: test23:
679; CHECK-FISL:       # %bb.0: # %entry
680; CHECK-FISL-NEXT:    vcmpequh v4, v4, v5
681; CHECK-FISL-NEXT:    xxlor vs0, v4, v4
682; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
683; CHECK-FISL-NEXT:    blr
684;
685; CHECK-LE-LABEL: test23:
686; CHECK-LE:       # %bb.0: # %entry
687; CHECK-LE-NEXT:    vcmpequh v4, v4, v5
688; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
689; CHECK-LE-NEXT:    blr
690entry:
691  %m = icmp eq <8 x i16> %c, %d
692  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
693  ret <8 x i16> %v
694
695
696
697}
698
699define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
700; CHECK-LABEL: test24:
701; CHECK:       # %bb.0: # %entry
702; CHECK-NEXT:    vcmpequb v4, v4, v5
703; CHECK-NEXT:    xxsel v2, v3, v2, v4
704; CHECK-NEXT:    blr
705;
706; CHECK-REG-LABEL: test24:
707; CHECK-REG:       # %bb.0: # %entry
708; CHECK-REG-NEXT:    vcmpequb v4, v4, v5
709; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
710; CHECK-REG-NEXT:    blr
711;
712; CHECK-FISL-LABEL: test24:
713; CHECK-FISL:       # %bb.0: # %entry
714; CHECK-FISL-NEXT:    vcmpequb v4, v4, v5
715; CHECK-FISL-NEXT:    xxlor vs0, v4, v4
716; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
717; CHECK-FISL-NEXT:    blr
718;
719; CHECK-LE-LABEL: test24:
720; CHECK-LE:       # %bb.0: # %entry
721; CHECK-LE-NEXT:    vcmpequb v4, v4, v5
722; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
723; CHECK-LE-NEXT:    blr
724entry:
725  %m = icmp eq <16 x i8> %c, %d
726  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
727  ret <16 x i8> %v
728
729
730
731}
732
733define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
734; CHECK-LABEL: test25:
735; CHECK:       # %bb.0: # %entry
736; CHECK-NEXT:    xvcmpeqdp vs0, v4, v5
737; CHECK-NEXT:    xxsel v2, v3, v2, vs0
738; CHECK-NEXT:    blr
739;
740; CHECK-REG-LABEL: test25:
741; CHECK-REG:       # %bb.0: # %entry
742; CHECK-REG-NEXT:    xvcmpeqdp vs0, v4, v5
743; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
744; CHECK-REG-NEXT:    blr
745;
746; CHECK-FISL-LABEL: test25:
747; CHECK-FISL:       # %bb.0: # %entry
748; CHECK-FISL-NEXT:    xvcmpeqdp vs0, v4, v5
749; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
750; CHECK-FISL-NEXT:    blr
751;
752; CHECK-LE-LABEL: test25:
753; CHECK-LE:       # %bb.0: # %entry
754; CHECK-LE-NEXT:    xvcmpeqdp v4, v4, v5
755; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
756; CHECK-LE-NEXT:    blr
757entry:
758  %m = fcmp oeq <2 x double> %c, %d
759  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
760  ret <2 x double> %v
761
762
763}
764
765define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
766; CHECK-LABEL: test26:
767; CHECK:       # %bb.0:
768; CHECK-NEXT:    addi r3, r1, -32
769; CHECK-NEXT:    stxvd2x v3, 0, r3
770; CHECK-NEXT:    addi r3, r1, -48
771; CHECK-NEXT:    stxvd2x v2, 0, r3
772; CHECK-NEXT:    ld r3, -24(r1)
773; CHECK-NEXT:    ld r4, -40(r1)
774; CHECK-NEXT:    add r3, r4, r3
775; CHECK-NEXT:    ld r4, -48(r1)
776; CHECK-NEXT:    std r3, -8(r1)
777; CHECK-NEXT:    ld r3, -32(r1)
778; CHECK-NEXT:    add r3, r4, r3
779; CHECK-NEXT:    std r3, -16(r1)
780; CHECK-NEXT:    addi r3, r1, -16
781; CHECK-NEXT:    lxvd2x v2, 0, r3
782; CHECK-NEXT:    blr
783;
784; CHECK-REG-LABEL: test26:
785; CHECK-REG:       # %bb.0:
786; CHECK-REG-NEXT:    addi r3, r1, -32
787; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
788; CHECK-REG-NEXT:    addi r3, r1, -48
789; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
790; CHECK-REG-NEXT:    ld r3, -24(r1)
791; CHECK-REG-NEXT:    ld r4, -40(r1)
792; CHECK-REG-NEXT:    add r3, r4, r3
793; CHECK-REG-NEXT:    ld r4, -48(r1)
794; CHECK-REG-NEXT:    std r3, -8(r1)
795; CHECK-REG-NEXT:    ld r3, -32(r1)
796; CHECK-REG-NEXT:    add r3, r4, r3
797; CHECK-REG-NEXT:    std r3, -16(r1)
798; CHECK-REG-NEXT:    addi r3, r1, -16
799; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
800; CHECK-REG-NEXT:    blr
801;
802; CHECK-FISL-LABEL: test26:
803; CHECK-FISL:       # %bb.0:
804; CHECK-FISL-NEXT:    addi r3, r1, -32
805; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
806; CHECK-FISL-NEXT:    addi r3, r1, -48
807; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
808; CHECK-FISL-NEXT:    ld r4, -24(r1)
809; CHECK-FISL-NEXT:    ld r3, -40(r1)
810; CHECK-FISL-NEXT:    add r3, r3, r4
811; CHECK-FISL-NEXT:    std r3, -8(r1)
812; CHECK-FISL-NEXT:    ld r4, -32(r1)
813; CHECK-FISL-NEXT:    ld r3, -48(r1)
814; CHECK-FISL-NEXT:    add r3, r3, r4
815; CHECK-FISL-NEXT:    std r3, -16(r1)
816; CHECK-FISL-NEXT:    addi r3, r1, -16
817; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
818; CHECK-FISL-NEXT:    blr
819;
820; CHECK-LE-LABEL: test26:
821; CHECK-LE:       # %bb.0:
822; CHECK-LE-NEXT:    vaddudm v2, v2, v3
823; CHECK-LE-NEXT:    blr
824  %v = add <2 x i64> %a, %b
825  ret <2 x i64> %v
826
827
828; Make sure we use only two stores (one for each operand).
829
830; FIXME: The code quality here is not good; just make sure we do something for now.
831
832}
833
834define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
835; CHECK-LABEL: test27:
836; CHECK:       # %bb.0:
837; CHECK-NEXT:    xxland v2, v2, v3
838; CHECK-NEXT:    blr
839;
840; CHECK-REG-LABEL: test27:
841; CHECK-REG:       # %bb.0:
842; CHECK-REG-NEXT:    xxland v2, v2, v3
843; CHECK-REG-NEXT:    blr
844;
845; CHECK-FISL-LABEL: test27:
846; CHECK-FISL:       # %bb.0:
847; CHECK-FISL-NEXT:    xxland v2, v2, v3
848; CHECK-FISL-NEXT:    blr
849;
850; CHECK-LE-LABEL: test27:
851; CHECK-LE:       # %bb.0:
852; CHECK-LE-NEXT:    xxland v2, v2, v3
853; CHECK-LE-NEXT:    blr
854  %v = and <2 x i64> %a, %b
855  ret <2 x i64> %v
856
857
858}
859
860define <2 x double> @test28(ptr %a) {
861; CHECK-LABEL: test28:
862; CHECK:       # %bb.0:
863; CHECK-NEXT:    lxvd2x v2, 0, r3
864; CHECK-NEXT:    blr
865;
866; CHECK-REG-LABEL: test28:
867; CHECK-REG:       # %bb.0:
868; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
869; CHECK-REG-NEXT:    blr
870;
871; CHECK-FISL-LABEL: test28:
872; CHECK-FISL:       # %bb.0:
873; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
874; CHECK-FISL-NEXT:    blr
875;
876; CHECK-LE-LABEL: test28:
877; CHECK-LE:       # %bb.0:
878; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
879; CHECK-LE-NEXT:    xxswapd v2, vs0
880; CHECK-LE-NEXT:    blr
881  %v = load <2 x double>, ptr %a, align 16
882  ret <2 x double> %v
883
884
885}
886
887define void @test29(ptr %a, <2 x double> %b) {
888; CHECK-LABEL: test29:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    stxvd2x v2, 0, r3
891; CHECK-NEXT:    blr
892;
893; CHECK-REG-LABEL: test29:
894; CHECK-REG:       # %bb.0:
895; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
896; CHECK-REG-NEXT:    blr
897;
898; CHECK-FISL-LABEL: test29:
899; CHECK-FISL:       # %bb.0:
900; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
901; CHECK-FISL-NEXT:    blr
902;
903; CHECK-LE-LABEL: test29:
904; CHECK-LE:       # %bb.0:
905; CHECK-LE-NEXT:    xxswapd vs0, v2
906; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
907; CHECK-LE-NEXT:    blr
908  store <2 x double> %b, ptr %a, align 16
909  ret void
910
911
912}
913
914define <2 x double> @test28u(ptr %a) {
915; CHECK-LABEL: test28u:
916; CHECK:       # %bb.0:
917; CHECK-NEXT:    lxvd2x v2, 0, r3
918; CHECK-NEXT:    blr
919;
920; CHECK-REG-LABEL: test28u:
921; CHECK-REG:       # %bb.0:
922; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
923; CHECK-REG-NEXT:    blr
924;
925; CHECK-FISL-LABEL: test28u:
926; CHECK-FISL:       # %bb.0:
927; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
928; CHECK-FISL-NEXT:    blr
929;
930; CHECK-LE-LABEL: test28u:
931; CHECK-LE:       # %bb.0:
932; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
933; CHECK-LE-NEXT:    xxswapd v2, vs0
934; CHECK-LE-NEXT:    blr
935  %v = load <2 x double>, ptr %a, align 8
936  ret <2 x double> %v
937
938
939}
940
941define void @test29u(ptr %a, <2 x double> %b) {
942; CHECK-LABEL: test29u:
943; CHECK:       # %bb.0:
944; CHECK-NEXT:    stxvd2x v2, 0, r3
945; CHECK-NEXT:    blr
946;
947; CHECK-REG-LABEL: test29u:
948; CHECK-REG:       # %bb.0:
949; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
950; CHECK-REG-NEXT:    blr
951;
952; CHECK-FISL-LABEL: test29u:
953; CHECK-FISL:       # %bb.0:
954; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
955; CHECK-FISL-NEXT:    blr
956;
957; CHECK-LE-LABEL: test29u:
958; CHECK-LE:       # %bb.0:
959; CHECK-LE-NEXT:    xxswapd vs0, v2
960; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
961; CHECK-LE-NEXT:    blr
962  store <2 x double> %b, ptr %a, align 8
963  ret void
964
965
966}
967
968define <2 x i64> @test30(ptr %a) {
969; CHECK-LABEL: test30:
970; CHECK:       # %bb.0:
971; CHECK-NEXT:    lxvd2x v2, 0, r3
972; CHECK-NEXT:    blr
973;
974; CHECK-REG-LABEL: test30:
975; CHECK-REG:       # %bb.0:
976; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
977; CHECK-REG-NEXT:    blr
978;
979; CHECK-FISL-LABEL: test30:
980; CHECK-FISL:       # %bb.0:
981; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
982; CHECK-FISL-NEXT:    blr
983;
984; CHECK-LE-LABEL: test30:
985; CHECK-LE:       # %bb.0:
986; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
987; CHECK-LE-NEXT:    xxswapd v2, vs0
988; CHECK-LE-NEXT:    blr
989  %v = load <2 x i64>, ptr %a, align 16
990  ret <2 x i64> %v
991
992
993
994}
995
996define void @test31(ptr %a, <2 x i64> %b) {
997; CHECK-LABEL: test31:
998; CHECK:       # %bb.0:
999; CHECK-NEXT:    stxvd2x v2, 0, r3
1000; CHECK-NEXT:    blr
1001;
1002; CHECK-REG-LABEL: test31:
1003; CHECK-REG:       # %bb.0:
1004; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1005; CHECK-REG-NEXT:    blr
1006;
1007; CHECK-FISL-LABEL: test31:
1008; CHECK-FISL:       # %bb.0:
1009; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1010; CHECK-FISL-NEXT:    blr
1011;
1012; CHECK-LE-LABEL: test31:
1013; CHECK-LE:       # %bb.0:
1014; CHECK-LE-NEXT:    xxswapd vs0, v2
1015; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1016; CHECK-LE-NEXT:    blr
1017  store <2 x i64> %b, ptr %a, align 16
1018  ret void
1019
1020
1021}
1022
1023define <4 x float> @test32(ptr %a) {
1024; CHECK-LABEL: test32:
1025; CHECK:       # %bb.0:
1026; CHECK-NEXT:    lxvw4x v2, 0, r3
1027; CHECK-NEXT:    blr
1028;
1029; CHECK-REG-LABEL: test32:
1030; CHECK-REG:       # %bb.0:
1031; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1032; CHECK-REG-NEXT:    blr
1033;
1034; CHECK-FISL-LABEL: test32:
1035; CHECK-FISL:       # %bb.0:
1036; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1037; CHECK-FISL-NEXT:    blr
1038;
1039; CHECK-LE-LABEL: test32:
1040; CHECK-LE:       # %bb.0:
1041; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
1042; CHECK-LE-NEXT:    xxswapd v2, vs0
1043; CHECK-LE-NEXT:    blr
1044  %v = load <4 x float>, ptr %a, align 16
1045  ret <4 x float> %v
1046
1047
1048
1049}
1050
1051define void @test33(ptr %a, <4 x float> %b) {
1052; CHECK-LABEL: test33:
1053; CHECK:       # %bb.0:
1054; CHECK-NEXT:    stxvw4x v2, 0, r3
1055; CHECK-NEXT:    blr
1056;
1057; CHECK-REG-LABEL: test33:
1058; CHECK-REG:       # %bb.0:
1059; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1060; CHECK-REG-NEXT:    blr
1061;
1062; CHECK-FISL-LABEL: test33:
1063; CHECK-FISL:       # %bb.0:
1064; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1065; CHECK-FISL-NEXT:    blr
1066;
1067; CHECK-LE-LABEL: test33:
1068; CHECK-LE:       # %bb.0:
1069; CHECK-LE-NEXT:    xxswapd vs0, v2
1070; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1071; CHECK-LE-NEXT:    blr
1072  store <4 x float> %b, ptr %a, align 16
1073  ret void
1074
1075
1076
1077}
1078
1079define <4 x float> @test32u(ptr %a) {
1080; CHECK-LABEL: test32u:
1081; CHECK:       # %bb.0:
1082; CHECK-NEXT:    li r4, 15
1083; CHECK-NEXT:    lvsl v3, 0, r3
1084; CHECK-NEXT:    lvx v2, r3, r4
1085; CHECK-NEXT:    lvx v4, 0, r3
1086; CHECK-NEXT:    vperm v2, v4, v2, v3
1087; CHECK-NEXT:    blr
1088;
1089; CHECK-REG-LABEL: test32u:
1090; CHECK-REG:       # %bb.0:
1091; CHECK-REG-NEXT:    li r4, 15
1092; CHECK-REG-NEXT:    lvsl v3, 0, r3
1093; CHECK-REG-NEXT:    lvx v2, r3, r4
1094; CHECK-REG-NEXT:    lvx v4, 0, r3
1095; CHECK-REG-NEXT:    vperm v2, v4, v2, v3
1096; CHECK-REG-NEXT:    blr
1097;
1098; CHECK-FISL-LABEL: test32u:
1099; CHECK-FISL:       # %bb.0:
1100; CHECK-FISL-NEXT:    li r4, 15
1101; CHECK-FISL-NEXT:    lvx v3, r3, r4
1102; CHECK-FISL-NEXT:    lvsl v4, 0, r3
1103; CHECK-FISL-NEXT:    lvx v2, 0, r3
1104; CHECK-FISL-NEXT:    vperm v2, v2, v3, v4
1105; CHECK-FISL-NEXT:    blr
1106;
1107; CHECK-LE-LABEL: test32u:
1108; CHECK-LE:       # %bb.0:
1109; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
1110; CHECK-LE-NEXT:    xxswapd v2, vs0
1111; CHECK-LE-NEXT:    blr
1112  %v = load <4 x float>, ptr %a, align 8
1113  ret <4 x float> %v
1114
1115
1116}
1117
1118define void @test33u(ptr %a, <4 x float> %b) {
1119; CHECK-LABEL: test33u:
1120; CHECK:       # %bb.0:
1121; CHECK-NEXT:    stxvw4x v2, 0, r3
1122; CHECK-NEXT:    blr
1123;
1124; CHECK-REG-LABEL: test33u:
1125; CHECK-REG:       # %bb.0:
1126; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1127; CHECK-REG-NEXT:    blr
1128;
1129; CHECK-FISL-LABEL: test33u:
1130; CHECK-FISL:       # %bb.0:
1131; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1132; CHECK-FISL-NEXT:    blr
1133;
1134; CHECK-LE-LABEL: test33u:
1135; CHECK-LE:       # %bb.0:
1136; CHECK-LE-NEXT:    xxswapd vs0, v2
1137; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1138; CHECK-LE-NEXT:    blr
1139  store <4 x float> %b, ptr %a, align 8
1140  ret void
1141
1142
1143
1144}
1145
1146define <4 x i32> @test34(ptr %a) {
1147; CHECK-LABEL: test34:
1148; CHECK:       # %bb.0:
1149; CHECK-NEXT:    lxvw4x v2, 0, r3
1150; CHECK-NEXT:    blr
1151;
1152; CHECK-REG-LABEL: test34:
1153; CHECK-REG:       # %bb.0:
1154; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1155; CHECK-REG-NEXT:    blr
1156;
1157; CHECK-FISL-LABEL: test34:
1158; CHECK-FISL:       # %bb.0:
1159; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1160; CHECK-FISL-NEXT:    blr
1161;
1162; CHECK-LE-LABEL: test34:
1163; CHECK-LE:       # %bb.0:
1164; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
1165; CHECK-LE-NEXT:    xxswapd v2, vs0
1166; CHECK-LE-NEXT:    blr
1167  %v = load <4 x i32>, ptr %a, align 16
1168  ret <4 x i32> %v
1169
1170
1171
1172}
1173
1174define void @test35(ptr %a, <4 x i32> %b) {
1175; CHECK-LABEL: test35:
1176; CHECK:       # %bb.0:
1177; CHECK-NEXT:    stxvw4x v2, 0, r3
1178; CHECK-NEXT:    blr
1179;
1180; CHECK-REG-LABEL: test35:
1181; CHECK-REG:       # %bb.0:
1182; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1183; CHECK-REG-NEXT:    blr
1184;
1185; CHECK-FISL-LABEL: test35:
1186; CHECK-FISL:       # %bb.0:
1187; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1188; CHECK-FISL-NEXT:    blr
1189;
1190; CHECK-LE-LABEL: test35:
1191; CHECK-LE:       # %bb.0:
1192; CHECK-LE-NEXT:    xxswapd vs0, v2
1193; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1194; CHECK-LE-NEXT:    blr
1195  store <4 x i32> %b, ptr %a, align 16
1196  ret void
1197
1198
1199
1200}
1201
1202define <2 x double> @test40(<2 x i64> %a) {
1203; CHECK-LABEL: test40:
1204; CHECK:       # %bb.0:
1205; CHECK-NEXT:    xvcvuxddp v2, v2
1206; CHECK-NEXT:    blr
1207;
1208; CHECK-REG-LABEL: test40:
1209; CHECK-REG:       # %bb.0:
1210; CHECK-REG-NEXT:    xvcvuxddp v2, v2
1211; CHECK-REG-NEXT:    blr
1212;
1213; CHECK-FISL-LABEL: test40:
1214; CHECK-FISL:       # %bb.0:
1215; CHECK-FISL-NEXT:    xvcvuxddp v2, v2
1216; CHECK-FISL-NEXT:    blr
1217;
1218; CHECK-LE-LABEL: test40:
1219; CHECK-LE:       # %bb.0:
1220; CHECK-LE-NEXT:    xvcvuxddp v2, v2
1221; CHECK-LE-NEXT:    blr
1222  %v = uitofp <2 x i64> %a to <2 x double>
1223  ret <2 x double> %v
1224
1225
1226}
1227
1228define <2 x double> @test41(<2 x i64> %a) {
1229; CHECK-LABEL: test41:
1230; CHECK:       # %bb.0:
1231; CHECK-NEXT:    xvcvsxddp v2, v2
1232; CHECK-NEXT:    blr
1233;
1234; CHECK-REG-LABEL: test41:
1235; CHECK-REG:       # %bb.0:
1236; CHECK-REG-NEXT:    xvcvsxddp v2, v2
1237; CHECK-REG-NEXT:    blr
1238;
1239; CHECK-FISL-LABEL: test41:
1240; CHECK-FISL:       # %bb.0:
1241; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
1242; CHECK-FISL-NEXT:    blr
1243;
1244; CHECK-LE-LABEL: test41:
1245; CHECK-LE:       # %bb.0:
1246; CHECK-LE-NEXT:    xvcvsxddp v2, v2
1247; CHECK-LE-NEXT:    blr
1248  %v = sitofp <2 x i64> %a to <2 x double>
1249  ret <2 x double> %v
1250
1251
1252}
1253
1254define <2 x i64> @test42(<2 x double> %a) {
1255; CHECK-LABEL: test42:
1256; CHECK:       # %bb.0:
1257; CHECK-NEXT:    xvcvdpuxds v2, v2
1258; CHECK-NEXT:    blr
1259;
1260; CHECK-REG-LABEL: test42:
1261; CHECK-REG:       # %bb.0:
1262; CHECK-REG-NEXT:    xvcvdpuxds v2, v2
1263; CHECK-REG-NEXT:    blr
1264;
1265; CHECK-FISL-LABEL: test42:
1266; CHECK-FISL:       # %bb.0:
1267; CHECK-FISL-NEXT:    xvcvdpuxds v2, v2
1268; CHECK-FISL-NEXT:    blr
1269;
1270; CHECK-LE-LABEL: test42:
1271; CHECK-LE:       # %bb.0:
1272; CHECK-LE-NEXT:    xvcvdpuxds v2, v2
1273; CHECK-LE-NEXT:    blr
1274  %v = fptoui <2 x double> %a to <2 x i64>
1275  ret <2 x i64> %v
1276
1277
1278}
1279
1280define <2 x i64> @test43(<2 x double> %a) {
1281; CHECK-LABEL: test43:
1282; CHECK:       # %bb.0:
1283; CHECK-NEXT:    xvcvdpsxds v2, v2
1284; CHECK-NEXT:    blr
1285;
1286; CHECK-REG-LABEL: test43:
1287; CHECK-REG:       # %bb.0:
1288; CHECK-REG-NEXT:    xvcvdpsxds v2, v2
1289; CHECK-REG-NEXT:    blr
1290;
1291; CHECK-FISL-LABEL: test43:
1292; CHECK-FISL:       # %bb.0:
1293; CHECK-FISL-NEXT:    xvcvdpsxds v2, v2
1294; CHECK-FISL-NEXT:    blr
1295;
1296; CHECK-LE-LABEL: test43:
1297; CHECK-LE:       # %bb.0:
1298; CHECK-LE-NEXT:    xvcvdpsxds v2, v2
1299; CHECK-LE-NEXT:    blr
1300  %v = fptosi <2 x double> %a to <2 x i64>
1301  ret <2 x i64> %v
1302
1303
1304}
1305
1306define <2 x float> @test44(<2 x i64> %a) {
1307; CHECK-LABEL: test44:
1308; CHECK:       # %bb.0:
1309; CHECK-NEXT:    addi r3, r1, -16
1310; CHECK-NEXT:    stxvd2x v2, 0, r3
1311; CHECK-NEXT:    ld r3, -8(r1)
1312; CHECK-NEXT:    std r3, -24(r1)
1313; CHECK-NEXT:    ld r3, -16(r1)
1314; CHECK-NEXT:    lfd f0, -24(r1)
1315; CHECK-NEXT:    std r3, -32(r1)
1316; CHECK-NEXT:    addi r3, r1, -48
1317; CHECK-NEXT:    fcfidus f0, f0
1318; CHECK-NEXT:    stfs f0, -48(r1)
1319; CHECK-NEXT:    lfd f0, -32(r1)
1320; CHECK-NEXT:    fcfidus f0, f0
1321; CHECK-NEXT:    stfs f0, -64(r1)
1322; CHECK-NEXT:    lxvw4x vs0, 0, r3
1323; CHECK-NEXT:    addi r3, r1, -64
1324; CHECK-NEXT:    lxvw4x vs1, 0, r3
1325; CHECK-NEXT:    xxmrghw v2, vs1, vs0
1326; CHECK-NEXT:    blr
1327;
1328; CHECK-REG-LABEL: test44:
1329; CHECK-REG:       # %bb.0:
1330; CHECK-REG-NEXT:    addi r3, r1, -16
1331; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1332; CHECK-REG-NEXT:    ld r3, -8(r1)
1333; CHECK-REG-NEXT:    std r3, -24(r1)
1334; CHECK-REG-NEXT:    ld r3, -16(r1)
1335; CHECK-REG-NEXT:    lfd f0, -24(r1)
1336; CHECK-REG-NEXT:    std r3, -32(r1)
1337; CHECK-REG-NEXT:    addi r3, r1, -48
1338; CHECK-REG-NEXT:    fcfidus f0, f0
1339; CHECK-REG-NEXT:    stfs f0, -48(r1)
1340; CHECK-REG-NEXT:    lfd f0, -32(r1)
1341; CHECK-REG-NEXT:    fcfidus f0, f0
1342; CHECK-REG-NEXT:    stfs f0, -64(r1)
1343; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
1344; CHECK-REG-NEXT:    addi r3, r1, -64
1345; CHECK-REG-NEXT:    lxvw4x vs1, 0, r3
1346; CHECK-REG-NEXT:    xxmrghw v2, vs1, vs0
1347; CHECK-REG-NEXT:    blr
1348;
1349; CHECK-FISL-LABEL: test44:
1350; CHECK-FISL:       # %bb.0:
1351; CHECK-FISL-NEXT:    addi r3, r1, -16
1352; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1353; CHECK-FISL-NEXT:    ld r3, -8(r1)
1354; CHECK-FISL-NEXT:    std r3, -24(r1)
1355; CHECK-FISL-NEXT:    ld r3, -16(r1)
1356; CHECK-FISL-NEXT:    std r3, -32(r1)
1357; CHECK-FISL-NEXT:    lfd f0, -24(r1)
1358; CHECK-FISL-NEXT:    fcfidus f0, f0
1359; CHECK-FISL-NEXT:    stfs f0, -48(r1)
1360; CHECK-FISL-NEXT:    lfd f0, -32(r1)
1361; CHECK-FISL-NEXT:    fcfidus f0, f0
1362; CHECK-FISL-NEXT:    stfs f0, -64(r1)
1363; CHECK-FISL-NEXT:    addi r3, r1, -48
1364; CHECK-FISL-NEXT:    lxvw4x vs1, 0, r3
1365; CHECK-FISL-NEXT:    addi r3, r1, -64
1366; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
1367; CHECK-FISL-NEXT:    xxmrghw v2, vs0, vs1
1368; CHECK-FISL-NEXT:    blr
1369;
1370; CHECK-LE-LABEL: test44:
1371; CHECK-LE:       # %bb.0:
1372; CHECK-LE-NEXT:    xxswapd vs0, v2
1373; CHECK-LE-NEXT:    xscvuxdsp f1, v2
1374; CHECK-LE-NEXT:    xscvuxdsp f0, f0
1375; CHECK-LE-NEXT:    xscvdpspn vs1, f1
1376; CHECK-LE-NEXT:    xscvdpspn vs0, f0
1377; CHECK-LE-NEXT:    xxmrghw v2, vs1, vs0
1378; CHECK-LE-NEXT:    blr
1379  %v = uitofp <2 x i64> %a to <2 x float>
1380  ret <2 x float> %v
1381
1382; FIXME: The code quality here looks pretty bad.
1383}
1384
1385define <2 x float> @test45(<2 x i64> %a) {
1386; CHECK-LABEL: test45:
1387; CHECK:       # %bb.0:
1388; CHECK-NEXT:    addi r3, r1, -16
1389; CHECK-NEXT:    stxvd2x v2, 0, r3
1390; CHECK-NEXT:    ld r3, -8(r1)
1391; CHECK-NEXT:    std r3, -24(r1)
1392; CHECK-NEXT:    ld r3, -16(r1)
1393; CHECK-NEXT:    lfd f0, -24(r1)
1394; CHECK-NEXT:    std r3, -32(r1)
1395; CHECK-NEXT:    addi r3, r1, -48
1396; CHECK-NEXT:    fcfids f0, f0
1397; CHECK-NEXT:    stfs f0, -48(r1)
1398; CHECK-NEXT:    lfd f0, -32(r1)
1399; CHECK-NEXT:    fcfids f0, f0
1400; CHECK-NEXT:    stfs f0, -64(r1)
1401; CHECK-NEXT:    lxvw4x vs0, 0, r3
1402; CHECK-NEXT:    addi r3, r1, -64
1403; CHECK-NEXT:    lxvw4x vs1, 0, r3
1404; CHECK-NEXT:    xxmrghw v2, vs1, vs0
1405; CHECK-NEXT:    blr
1406;
1407; CHECK-REG-LABEL: test45:
1408; CHECK-REG:       # %bb.0:
1409; CHECK-REG-NEXT:    addi r3, r1, -16
1410; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1411; CHECK-REG-NEXT:    ld r3, -8(r1)
1412; CHECK-REG-NEXT:    std r3, -24(r1)
1413; CHECK-REG-NEXT:    ld r3, -16(r1)
1414; CHECK-REG-NEXT:    lfd f0, -24(r1)
1415; CHECK-REG-NEXT:    std r3, -32(r1)
1416; CHECK-REG-NEXT:    addi r3, r1, -48
1417; CHECK-REG-NEXT:    fcfids f0, f0
1418; CHECK-REG-NEXT:    stfs f0, -48(r1)
1419; CHECK-REG-NEXT:    lfd f0, -32(r1)
1420; CHECK-REG-NEXT:    fcfids f0, f0
1421; CHECK-REG-NEXT:    stfs f0, -64(r1)
1422; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
1423; CHECK-REG-NEXT:    addi r3, r1, -64
1424; CHECK-REG-NEXT:    lxvw4x vs1, 0, r3
1425; CHECK-REG-NEXT:    xxmrghw v2, vs1, vs0
1426; CHECK-REG-NEXT:    blr
1427;
1428; CHECK-FISL-LABEL: test45:
1429; CHECK-FISL:       # %bb.0:
1430; CHECK-FISL-NEXT:    addi r3, r1, -16
1431; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1432; CHECK-FISL-NEXT:    ld r3, -8(r1)
1433; CHECK-FISL-NEXT:    std r3, -24(r1)
1434; CHECK-FISL-NEXT:    ld r3, -16(r1)
1435; CHECK-FISL-NEXT:    std r3, -32(r1)
1436; CHECK-FISL-NEXT:    lfd f0, -24(r1)
1437; CHECK-FISL-NEXT:    fcfids f0, f0
1438; CHECK-FISL-NEXT:    stfs f0, -48(r1)
1439; CHECK-FISL-NEXT:    lfd f0, -32(r1)
1440; CHECK-FISL-NEXT:    fcfids f0, f0
1441; CHECK-FISL-NEXT:    stfs f0, -64(r1)
1442; CHECK-FISL-NEXT:    addi r3, r1, -48
1443; CHECK-FISL-NEXT:    lxvw4x vs1, 0, r3
1444; CHECK-FISL-NEXT:    addi r3, r1, -64
1445; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
1446; CHECK-FISL-NEXT:    xxmrghw v2, vs0, vs1
1447; CHECK-FISL-NEXT:    blr
1448;
1449; CHECK-LE-LABEL: test45:
1450; CHECK-LE:       # %bb.0:
1451; CHECK-LE-NEXT:    xxswapd vs0, v2
1452; CHECK-LE-NEXT:    xscvsxdsp f1, v2
1453; CHECK-LE-NEXT:    xscvsxdsp f0, f0
1454; CHECK-LE-NEXT:    xscvdpspn vs1, f1
1455; CHECK-LE-NEXT:    xscvdpspn vs0, f0
1456; CHECK-LE-NEXT:    xxmrghw v2, vs1, vs0
1457; CHECK-LE-NEXT:    blr
1458  %v = sitofp <2 x i64> %a to <2 x float>
1459  ret <2 x float> %v
1460
1461; FIXME: The code quality here looks pretty bad.
1462}
1463
1464define <2 x i64> @test46(<2 x float> %a) {
1465; CHECK-LABEL: test46:
1466; CHECK:       # %bb.0:
1467; CHECK-NEXT:    addi r3, r1, -48
1468; CHECK-NEXT:    stxvw4x v2, 0, r3
1469; CHECK-NEXT:    lfs f0, -44(r1)
1470; CHECK-NEXT:    xscvdpuxds f0, f0
1471; CHECK-NEXT:    stfd f0, -32(r1)
1472; CHECK-NEXT:    lfs f0, -48(r1)
1473; CHECK-NEXT:    ld r3, -32(r1)
1474; CHECK-NEXT:    xscvdpuxds f0, f0
1475; CHECK-NEXT:    std r3, -8(r1)
1476; CHECK-NEXT:    stfd f0, -24(r1)
1477; CHECK-NEXT:    ld r3, -24(r1)
1478; CHECK-NEXT:    std r3, -16(r1)
1479; CHECK-NEXT:    addi r3, r1, -16
1480; CHECK-NEXT:    lxvd2x v2, 0, r3
1481; CHECK-NEXT:    blr
1482;
1483; CHECK-REG-LABEL: test46:
1484; CHECK-REG:       # %bb.0:
1485; CHECK-REG-NEXT:    addi r3, r1, -48
1486; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1487; CHECK-REG-NEXT:    lfs f0, -44(r1)
1488; CHECK-REG-NEXT:    xscvdpuxds f0, f0
1489; CHECK-REG-NEXT:    stfd f0, -32(r1)
1490; CHECK-REG-NEXT:    lfs f0, -48(r1)
1491; CHECK-REG-NEXT:    ld r3, -32(r1)
1492; CHECK-REG-NEXT:    xscvdpuxds f0, f0
1493; CHECK-REG-NEXT:    std r3, -8(r1)
1494; CHECK-REG-NEXT:    stfd f0, -24(r1)
1495; CHECK-REG-NEXT:    ld r3, -24(r1)
1496; CHECK-REG-NEXT:    std r3, -16(r1)
1497; CHECK-REG-NEXT:    addi r3, r1, -16
1498; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1499; CHECK-REG-NEXT:    blr
1500;
1501; CHECK-FISL-LABEL: test46:
1502; CHECK-FISL:       # %bb.0:
1503; CHECK-FISL-NEXT:    addi r3, r1, -48
1504; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1505; CHECK-FISL-NEXT:    lfs f0, -44(r1)
1506; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
1507; CHECK-FISL-NEXT:    stfd f0, -32(r1)
1508; CHECK-FISL-NEXT:    lfs f0, -48(r1)
1509; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
1510; CHECK-FISL-NEXT:    stfd f0, -24(r1)
1511; CHECK-FISL-NEXT:    ld r3, -32(r1)
1512; CHECK-FISL-NEXT:    std r3, -8(r1)
1513; CHECK-FISL-NEXT:    ld r3, -24(r1)
1514; CHECK-FISL-NEXT:    std r3, -16(r1)
1515; CHECK-FISL-NEXT:    addi r3, r1, -16
1516; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
1517; CHECK-FISL-NEXT:    blr
1518;
1519; CHECK-LE-LABEL: test46:
1520; CHECK-LE:       # %bb.0:
1521; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
1522; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
1523; CHECK-LE-NEXT:    xvcvdpuxds v2, vs0
1524; CHECK-LE-NEXT:    blr
1525  %v = fptoui <2 x float> %a to <2 x i64>
1526  ret <2 x i64> %v
1527
1528; FIXME: The code quality here looks pretty bad.
1529}
1530
1531define <2 x i64> @test47(<2 x float> %a) {
1532; CHECK-LABEL: test47:
1533; CHECK:       # %bb.0:
1534; CHECK-NEXT:    addi r3, r1, -48
1535; CHECK-NEXT:    stxvw4x v2, 0, r3
1536; CHECK-NEXT:    lfs f0, -44(r1)
1537; CHECK-NEXT:    xscvdpsxds f0, f0
1538; CHECK-NEXT:    stfd f0, -32(r1)
1539; CHECK-NEXT:    lfs f0, -48(r1)
1540; CHECK-NEXT:    ld r3, -32(r1)
1541; CHECK-NEXT:    xscvdpsxds f0, f0
1542; CHECK-NEXT:    std r3, -8(r1)
1543; CHECK-NEXT:    stfd f0, -24(r1)
1544; CHECK-NEXT:    ld r3, -24(r1)
1545; CHECK-NEXT:    std r3, -16(r1)
1546; CHECK-NEXT:    addi r3, r1, -16
1547; CHECK-NEXT:    lxvd2x v2, 0, r3
1548; CHECK-NEXT:    blr
1549;
1550; CHECK-REG-LABEL: test47:
1551; CHECK-REG:       # %bb.0:
1552; CHECK-REG-NEXT:    addi r3, r1, -48
1553; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1554; CHECK-REG-NEXT:    lfs f0, -44(r1)
1555; CHECK-REG-NEXT:    xscvdpsxds f0, f0
1556; CHECK-REG-NEXT:    stfd f0, -32(r1)
1557; CHECK-REG-NEXT:    lfs f0, -48(r1)
1558; CHECK-REG-NEXT:    ld r3, -32(r1)
1559; CHECK-REG-NEXT:    xscvdpsxds f0, f0
1560; CHECK-REG-NEXT:    std r3, -8(r1)
1561; CHECK-REG-NEXT:    stfd f0, -24(r1)
1562; CHECK-REG-NEXT:    ld r3, -24(r1)
1563; CHECK-REG-NEXT:    std r3, -16(r1)
1564; CHECK-REG-NEXT:    addi r3, r1, -16
1565; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1566; CHECK-REG-NEXT:    blr
1567;
1568; CHECK-FISL-LABEL: test47:
1569; CHECK-FISL:       # %bb.0:
1570; CHECK-FISL-NEXT:    addi r3, r1, -48
1571; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1572; CHECK-FISL-NEXT:    lfs f0, -44(r1)
1573; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
1574; CHECK-FISL-NEXT:    stfd f0, -32(r1)
1575; CHECK-FISL-NEXT:    lfs f0, -48(r1)
1576; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
1577; CHECK-FISL-NEXT:    stfd f0, -24(r1)
1578; CHECK-FISL-NEXT:    ld r3, -32(r1)
1579; CHECK-FISL-NEXT:    std r3, -8(r1)
1580; CHECK-FISL-NEXT:    ld r3, -24(r1)
1581; CHECK-FISL-NEXT:    std r3, -16(r1)
1582; CHECK-FISL-NEXT:    addi r3, r1, -16
1583; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
1584; CHECK-FISL-NEXT:    blr
1585;
1586; CHECK-LE-LABEL: test47:
1587; CHECK-LE:       # %bb.0:
1588; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
1589; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
1590; CHECK-LE-NEXT:    xvcvdpsxds v2, vs0
1591; CHECK-LE-NEXT:    blr
1592  %v = fptosi <2 x float> %a to <2 x i64>
1593  ret <2 x i64> %v
1594
1595; FIXME: The code quality here looks pretty bad.
1596}
1597
1598define <2 x double> @test50(ptr %a) {
1599; CHECK-LABEL: test50:
1600; CHECK:       # %bb.0:
1601; CHECK-NEXT:    lxvdsx v2, 0, r3
1602; CHECK-NEXT:    blr
1603;
1604; CHECK-REG-LABEL: test50:
1605; CHECK-REG:       # %bb.0:
1606; CHECK-REG-NEXT:    lxvdsx v2, 0, r3
1607; CHECK-REG-NEXT:    blr
1608;
1609; CHECK-FISL-LABEL: test50:
1610; CHECK-FISL:       # %bb.0:
1611; CHECK-FISL-NEXT:    lxvdsx v2, 0, r3
1612; CHECK-FISL-NEXT:    blr
1613;
1614; CHECK-LE-LABEL: test50:
1615; CHECK-LE:       # %bb.0:
1616; CHECK-LE-NEXT:    lxvdsx v2, 0, r3
1617; CHECK-LE-NEXT:    blr
1618  %v = load double, ptr %a, align 8
1619  %w = insertelement <2 x double> undef, double %v, i32 0
1620  %x = insertelement <2 x double> %w, double %v, i32 1
1621  ret <2 x double> %x
1622
1623
1624}
1625
1626define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
1627; CHECK-LABEL: test51:
1628; CHECK:       # %bb.0:
1629; CHECK-NEXT:    xxspltd v2, v2, 0
1630; CHECK-NEXT:    blr
1631;
1632; CHECK-REG-LABEL: test51:
1633; CHECK-REG:       # %bb.0:
1634; CHECK-REG-NEXT:    xxspltd v2, v2, 0
1635; CHECK-REG-NEXT:    blr
1636;
1637; CHECK-FISL-LABEL: test51:
1638; CHECK-FISL:       # %bb.0:
1639; CHECK-FISL-NEXT:    xxspltd v2, v2, 0
1640; CHECK-FISL-NEXT:    blr
1641;
1642; CHECK-LE-LABEL: test51:
1643; CHECK-LE:       # %bb.0:
1644; CHECK-LE-NEXT:    xxspltd v2, v2, 1
1645; CHECK-LE-NEXT:    blr
1646  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
1647  ret <2 x double> %v
1648
1649
1650}
1651
1652define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
1653; CHECK-LABEL: test52:
1654; CHECK:       # %bb.0:
1655; CHECK-NEXT:    xxmrghd v2, v2, v3
1656; CHECK-NEXT:    blr
1657;
1658; CHECK-REG-LABEL: test52:
1659; CHECK-REG:       # %bb.0:
1660; CHECK-REG-NEXT:    xxmrghd v2, v2, v3
1661; CHECK-REG-NEXT:    blr
1662;
1663; CHECK-FISL-LABEL: test52:
1664; CHECK-FISL:       # %bb.0:
1665; CHECK-FISL-NEXT:    xxmrghd v2, v2, v3
1666; CHECK-FISL-NEXT:    blr
1667;
1668; CHECK-LE-LABEL: test52:
1669; CHECK-LE:       # %bb.0:
1670; CHECK-LE-NEXT:    xxmrgld v2, v3, v2
1671; CHECK-LE-NEXT:    blr
1672  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
1673  ret <2 x double> %v
1674
1675
1676}
1677
1678define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
1679; CHECK-LABEL: test53:
1680; CHECK:       # %bb.0:
1681; CHECK-NEXT:    xxmrghd v2, v3, v2
1682; CHECK-NEXT:    blr
1683;
1684; CHECK-REG-LABEL: test53:
1685; CHECK-REG:       # %bb.0:
1686; CHECK-REG-NEXT:    xxmrghd v2, v3, v2
1687; CHECK-REG-NEXT:    blr
1688;
1689; CHECK-FISL-LABEL: test53:
1690; CHECK-FISL:       # %bb.0:
1691; CHECK-FISL-NEXT:    xxmrghd v2, v3, v2
1692; CHECK-FISL-NEXT:    blr
1693;
1694; CHECK-LE-LABEL: test53:
1695; CHECK-LE:       # %bb.0:
1696; CHECK-LE-NEXT:    xxmrgld v2, v2, v3
1697; CHECK-LE-NEXT:    blr
1698  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
1699  ret <2 x double> %v
1700
1701
1702}
1703
1704define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
1705; CHECK-LABEL: test54:
1706; CHECK:       # %bb.0:
1707; CHECK-NEXT:    xxpermdi v2, v2, v3, 2
1708; CHECK-NEXT:    blr
1709;
1710; CHECK-REG-LABEL: test54:
1711; CHECK-REG:       # %bb.0:
1712; CHECK-REG-NEXT:    xxpermdi v2, v2, v3, 2
1713; CHECK-REG-NEXT:    blr
1714;
1715; CHECK-FISL-LABEL: test54:
1716; CHECK-FISL:       # %bb.0:
1717; CHECK-FISL-NEXT:    xxpermdi v2, v2, v3, 2
1718; CHECK-FISL-NEXT:    blr
1719;
1720; CHECK-LE-LABEL: test54:
1721; CHECK-LE:       # %bb.0:
1722; CHECK-LE-NEXT:    xxpermdi v2, v3, v2, 2
1723; CHECK-LE-NEXT:    blr
1724  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
1725  ret <2 x double> %v
1726
1727
1728}
1729
1730define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
1731; CHECK-LABEL: test55:
1732; CHECK:       # %bb.0:
1733; CHECK-NEXT:    xxmrgld v2, v2, v3
1734; CHECK-NEXT:    blr
1735;
1736; CHECK-REG-LABEL: test55:
1737; CHECK-REG:       # %bb.0:
1738; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
1739; CHECK-REG-NEXT:    blr
1740;
1741; CHECK-FISL-LABEL: test55:
1742; CHECK-FISL:       # %bb.0:
1743; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
1744; CHECK-FISL-NEXT:    blr
1745;
1746; CHECK-LE-LABEL: test55:
1747; CHECK-LE:       # %bb.0:
1748; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
1749; CHECK-LE-NEXT:    blr
1750  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
1751  ret <2 x double> %v
1752
1753
1754}
1755
1756define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
1757; CHECK-LABEL: test56:
1758; CHECK:       # %bb.0:
1759; CHECK-NEXT:    xxmrgld v2, v2, v3
1760; CHECK-NEXT:    blr
1761;
1762; CHECK-REG-LABEL: test56:
1763; CHECK-REG:       # %bb.0:
1764; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
1765; CHECK-REG-NEXT:    blr
1766;
1767; CHECK-FISL-LABEL: test56:
1768; CHECK-FISL:       # %bb.0:
1769; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
1770; CHECK-FISL-NEXT:    blr
1771;
1772; CHECK-LE-LABEL: test56:
1773; CHECK-LE:       # %bb.0:
1774; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
1775; CHECK-LE-NEXT:    blr
1776  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
1777  ret <2 x i64> %v
1778
1779
1780}
1781
1782define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
1783; CHECK-LABEL: test60:
1784; CHECK:       # %bb.0:
1785; CHECK-NEXT:    addi r3, r1, -32
1786; CHECK-NEXT:    stxvd2x v3, 0, r3
1787; CHECK-NEXT:    addi r3, r1, -48
1788; CHECK-NEXT:    stxvd2x v2, 0, r3
1789; CHECK-NEXT:    lwz r3, -20(r1)
1790; CHECK-NEXT:    ld r4, -40(r1)
1791; CHECK-NEXT:    sld r3, r4, r3
1792; CHECK-NEXT:    ld r4, -48(r1)
1793; CHECK-NEXT:    std r3, -8(r1)
1794; CHECK-NEXT:    lwz r3, -28(r1)
1795; CHECK-NEXT:    sld r3, r4, r3
1796; CHECK-NEXT:    std r3, -16(r1)
1797; CHECK-NEXT:    addi r3, r1, -16
1798; CHECK-NEXT:    lxvd2x v2, 0, r3
1799; CHECK-NEXT:    blr
1800;
1801; CHECK-REG-LABEL: test60:
1802; CHECK-REG:       # %bb.0:
1803; CHECK-REG-NEXT:    addi r3, r1, -32
1804; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1805; CHECK-REG-NEXT:    addi r3, r1, -48
1806; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1807; CHECK-REG-NEXT:    lwz r3, -20(r1)
1808; CHECK-REG-NEXT:    ld r4, -40(r1)
1809; CHECK-REG-NEXT:    sld r3, r4, r3
1810; CHECK-REG-NEXT:    ld r4, -48(r1)
1811; CHECK-REG-NEXT:    std r3, -8(r1)
1812; CHECK-REG-NEXT:    lwz r3, -28(r1)
1813; CHECK-REG-NEXT:    sld r3, r4, r3
1814; CHECK-REG-NEXT:    std r3, -16(r1)
1815; CHECK-REG-NEXT:    addi r3, r1, -16
1816; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1817; CHECK-REG-NEXT:    blr
1818;
1819; CHECK-FISL-LABEL: test60:
1820; CHECK-FISL:       # %bb.0:
1821; CHECK-FISL-NEXT:    addi r3, r1, -32
1822; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1823; CHECK-FISL-NEXT:    addi r3, r1, -48
1824; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1825; CHECK-FISL-NEXT:    lwz r4, -20(r1)
1826; CHECK-FISL-NEXT:    ld r3, -40(r1)
1827; CHECK-FISL-NEXT:    sld r3, r3, r4
1828; CHECK-FISL-NEXT:    std r3, -8(r1)
1829; CHECK-FISL-NEXT:    lwz r4, -28(r1)
1830; CHECK-FISL-NEXT:    ld r3, -48(r1)
1831; CHECK-FISL-NEXT:    sld r3, r3, r4
1832; CHECK-FISL-NEXT:    std r3, -16(r1)
1833; CHECK-FISL-NEXT:    addi r3, r1, -16
1834; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
1835; CHECK-FISL-NEXT:    blr
1836;
1837; CHECK-LE-LABEL: test60:
1838; CHECK-LE:       # %bb.0:
1839; CHECK-LE-NEXT:    vsld v2, v2, v3
1840; CHECK-LE-NEXT:    blr
1841  %v = shl <2 x i64> %a, %b
1842  ret <2 x i64> %v
1843
1844; This should scalarize, and the current code quality is not good.
1845}
1846
1847define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
1848; CHECK-LABEL: test61:
1849; CHECK:       # %bb.0:
1850; CHECK-NEXT:    addi r3, r1, -32
1851; CHECK-NEXT:    stxvd2x v3, 0, r3
1852; CHECK-NEXT:    addi r3, r1, -48
1853; CHECK-NEXT:    stxvd2x v2, 0, r3
1854; CHECK-NEXT:    lwz r3, -20(r1)
1855; CHECK-NEXT:    ld r4, -40(r1)
1856; CHECK-NEXT:    srd r3, r4, r3
1857; CHECK-NEXT:    ld r4, -48(r1)
1858; CHECK-NEXT:    std r3, -8(r1)
1859; CHECK-NEXT:    lwz r3, -28(r1)
1860; CHECK-NEXT:    srd r3, r4, r3
1861; CHECK-NEXT:    std r3, -16(r1)
1862; CHECK-NEXT:    addi r3, r1, -16
1863; CHECK-NEXT:    lxvd2x v2, 0, r3
1864; CHECK-NEXT:    blr
1865;
1866; CHECK-REG-LABEL: test61:
1867; CHECK-REG:       # %bb.0:
1868; CHECK-REG-NEXT:    addi r3, r1, -32
1869; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1870; CHECK-REG-NEXT:    addi r3, r1, -48
1871; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1872; CHECK-REG-NEXT:    lwz r3, -20(r1)
1873; CHECK-REG-NEXT:    ld r4, -40(r1)
1874; CHECK-REG-NEXT:    srd r3, r4, r3
1875; CHECK-REG-NEXT:    ld r4, -48(r1)
1876; CHECK-REG-NEXT:    std r3, -8(r1)
1877; CHECK-REG-NEXT:    lwz r3, -28(r1)
1878; CHECK-REG-NEXT:    srd r3, r4, r3
1879; CHECK-REG-NEXT:    std r3, -16(r1)
1880; CHECK-REG-NEXT:    addi r3, r1, -16
1881; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1882; CHECK-REG-NEXT:    blr
1883;
1884; CHECK-FISL-LABEL: test61:
1885; CHECK-FISL:       # %bb.0:
1886; CHECK-FISL-NEXT:    addi r3, r1, -32
1887; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1888; CHECK-FISL-NEXT:    addi r3, r1, -48
1889; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1890; CHECK-FISL-NEXT:    lwz r4, -20(r1)
1891; CHECK-FISL-NEXT:    ld r3, -40(r1)
1892; CHECK-FISL-NEXT:    srd r3, r3, r4
1893; CHECK-FISL-NEXT:    std r3, -8(r1)
1894; CHECK-FISL-NEXT:    lwz r4, -28(r1)
1895; CHECK-FISL-NEXT:    ld r3, -48(r1)
1896; CHECK-FISL-NEXT:    srd r3, r3, r4
1897; CHECK-FISL-NEXT:    std r3, -16(r1)
1898; CHECK-FISL-NEXT:    addi r3, r1, -16
1899; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
1900; CHECK-FISL-NEXT:    blr
1901;
1902; CHECK-LE-LABEL: test61:
1903; CHECK-LE:       # %bb.0:
1904; CHECK-LE-NEXT:    vsrd v2, v2, v3
1905; CHECK-LE-NEXT:    blr
1906  %v = lshr <2 x i64> %a, %b
1907  ret <2 x i64> %v
1908
1909; This should scalarize, and the current code quality is not good.
1910}
1911
1912define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
1913; CHECK-LABEL: test62:
1914; CHECK:       # %bb.0:
1915; CHECK-NEXT:    addi r3, r1, -32
1916; CHECK-NEXT:    stxvd2x v3, 0, r3
1917; CHECK-NEXT:    addi r3, r1, -48
1918; CHECK-NEXT:    stxvd2x v2, 0, r3
1919; CHECK-NEXT:    lwz r3, -20(r1)
1920; CHECK-NEXT:    ld r4, -40(r1)
1921; CHECK-NEXT:    srad r3, r4, r3
1922; CHECK-NEXT:    ld r4, -48(r1)
1923; CHECK-NEXT:    std r3, -8(r1)
1924; CHECK-NEXT:    lwz r3, -28(r1)
1925; CHECK-NEXT:    srad r3, r4, r3
1926; CHECK-NEXT:    std r3, -16(r1)
1927; CHECK-NEXT:    addi r3, r1, -16
1928; CHECK-NEXT:    lxvd2x v2, 0, r3
1929; CHECK-NEXT:    blr
1930;
1931; CHECK-REG-LABEL: test62:
1932; CHECK-REG:       # %bb.0:
1933; CHECK-REG-NEXT:    addi r3, r1, -32
1934; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1935; CHECK-REG-NEXT:    addi r3, r1, -48
1936; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1937; CHECK-REG-NEXT:    lwz r3, -20(r1)
1938; CHECK-REG-NEXT:    ld r4, -40(r1)
1939; CHECK-REG-NEXT:    srad r3, r4, r3
1940; CHECK-REG-NEXT:    ld r4, -48(r1)
1941; CHECK-REG-NEXT:    std r3, -8(r1)
1942; CHECK-REG-NEXT:    lwz r3, -28(r1)
1943; CHECK-REG-NEXT:    srad r3, r4, r3
1944; CHECK-REG-NEXT:    std r3, -16(r1)
1945; CHECK-REG-NEXT:    addi r3, r1, -16
1946; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1947; CHECK-REG-NEXT:    blr
1948;
1949; CHECK-FISL-LABEL: test62:
1950; CHECK-FISL:       # %bb.0:
1951; CHECK-FISL-NEXT:    addi r3, r1, -32
1952; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1953; CHECK-FISL-NEXT:    addi r3, r1, -48
1954; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1955; CHECK-FISL-NEXT:    lwz r4, -20(r1)
1956; CHECK-FISL-NEXT:    ld r3, -40(r1)
1957; CHECK-FISL-NEXT:    srad r3, r3, r4
1958; CHECK-FISL-NEXT:    std r3, -8(r1)
1959; CHECK-FISL-NEXT:    lwz r4, -28(r1)
1960; CHECK-FISL-NEXT:    ld r3, -48(r1)
1961; CHECK-FISL-NEXT:    srad r3, r3, r4
1962; CHECK-FISL-NEXT:    std r3, -16(r1)
1963; CHECK-FISL-NEXT:    addi r3, r1, -16
1964; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
1965; CHECK-FISL-NEXT:    blr
1966;
1967; CHECK-LE-LABEL: test62:
1968; CHECK-LE:       # %bb.0:
1969; CHECK-LE-NEXT:    vsrad v2, v2, v3
1970; CHECK-LE-NEXT:    blr
1971  %v = ashr <2 x i64> %a, %b
1972  ret <2 x i64> %v
1973
1974; This should scalarize, and the current code quality is not good.
1975}
1976
1977define double @test63(<2 x double> %a) {
1978; CHECK-LABEL: test63:
1979; CHECK:       # %bb.0:
1980; CHECK-NEXT:    xxlor f1, v2, v2
1981; CHECK-NEXT:    blr
1982;
1983; CHECK-REG-LABEL: test63:
1984; CHECK-REG:       # %bb.0:
1985; CHECK-REG-NEXT:    xxlor f1, v2, v2
1986; CHECK-REG-NEXT:    blr
1987;
1988; CHECK-FISL-LABEL: test63:
1989; CHECK-FISL:       # %bb.0:
1990; CHECK-FISL-NEXT:    xxlor f1, v2, v2
1991; CHECK-FISL-NEXT:    blr
1992;
1993; CHECK-LE-LABEL: test63:
1994; CHECK-LE:       # %bb.0:
1995; CHECK-LE-NEXT:    xxswapd vs1, v2
1996; CHECK-LE-NEXT:    blr
1997  %v = extractelement <2 x double> %a, i32 0
1998  ret double %v
1999
2000
2001
2002}
2003
2004define double @test64(<2 x double> %a) {
2005; CHECK-LABEL: test64:
2006; CHECK:       # %bb.0:
2007; CHECK-NEXT:    xxswapd vs1, v2
2008; CHECK-NEXT:    blr
2009;
2010; CHECK-REG-LABEL: test64:
2011; CHECK-REG:       # %bb.0:
2012; CHECK-REG-NEXT:    xxswapd vs1, v2
2013; CHECK-REG-NEXT:    blr
2014;
2015; CHECK-FISL-LABEL: test64:
2016; CHECK-FISL:       # %bb.0:
2017; CHECK-FISL-NEXT:    xxswapd vs0, v2
2018; CHECK-FISL-NEXT:    fmr f1, f0
2019; CHECK-FISL-NEXT:    blr
2020;
2021; CHECK-LE-LABEL: test64:
2022; CHECK-LE:       # %bb.0:
2023; CHECK-LE-NEXT:    xxlor f1, v2, v2
2024; CHECK-LE-NEXT:    blr
2025  %v = extractelement <2 x double> %a, i32 1
2026  ret double %v
2027
2028
2029
2030}
2031
2032define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
2033; CHECK-LABEL: test65:
2034; CHECK:       # %bb.0:
2035; CHECK-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
2036; CHECK-NEXT:    vcmpequw v2, v2, v3
2037; CHECK-NEXT:    addi r3, r3, .LCPI59_0@toc@l
2038; CHECK-NEXT:    lxvw4x v3, 0, r3
2039; CHECK-NEXT:    vperm v3, v2, v2, v3
2040; CHECK-NEXT:    xxland v2, v3, v2
2041; CHECK-NEXT:    blr
2042;
2043; CHECK-REG-LABEL: test65:
2044; CHECK-REG:       # %bb.0:
2045; CHECK-REG-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
2046; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
2047; CHECK-REG-NEXT:    addi r3, r3, .LCPI59_0@toc@l
2048; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2049; CHECK-REG-NEXT:    vperm v3, v2, v2, v3
2050; CHECK-REG-NEXT:    xxland v2, v3, v2
2051; CHECK-REG-NEXT:    blr
2052;
2053; CHECK-FISL-LABEL: test65:
2054; CHECK-FISL:       # %bb.0:
2055; CHECK-FISL-NEXT:    vcmpequw v3, v2, v3
2056; CHECK-FISL-NEXT:    addis r3, r2, .LCPI59_0@toc@ha
2057; CHECK-FISL-NEXT:    addi r3, r3, .LCPI59_0@toc@l
2058; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
2059; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2
2060; CHECK-FISL-NEXT:    xxland v2, v2, v3
2061; CHECK-FISL-NEXT:    blr
2062;
2063; CHECK-LE-LABEL: test65:
2064; CHECK-LE:       # %bb.0:
2065; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
2066; CHECK-LE-NEXT:    blr
2067  %w = icmp eq <2 x i64> %a, %b
2068  ret <2 x i1> %w
2069
2070
2071
2072}
2073
2074define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
2075; CHECK-LABEL: test66:
2076; CHECK:       # %bb.0:
2077; CHECK-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
2078; CHECK-NEXT:    vcmpequw v2, v2, v3
2079; CHECK-NEXT:    addi r3, r3, .LCPI60_0@toc@l
2080; CHECK-NEXT:    lxvw4x v3, 0, r3
2081; CHECK-NEXT:    xxlnor v2, v2, v2
2082; CHECK-NEXT:    vperm v3, v2, v2, v3
2083; CHECK-NEXT:    xxlor v2, v3, v2
2084; CHECK-NEXT:    blr
2085;
2086; CHECK-REG-LABEL: test66:
2087; CHECK-REG:       # %bb.0:
2088; CHECK-REG-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
2089; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
2090; CHECK-REG-NEXT:    addi r3, r3, .LCPI60_0@toc@l
2091; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2092; CHECK-REG-NEXT:    xxlnor v2, v2, v2
2093; CHECK-REG-NEXT:    vperm v3, v2, v2, v3
2094; CHECK-REG-NEXT:    xxlor v2, v3, v2
2095; CHECK-REG-NEXT:    blr
2096;
2097; CHECK-FISL-LABEL: test66:
2098; CHECK-FISL:       # %bb.0:
2099; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3
2100; CHECK-FISL-NEXT:    xxlnor v3, v2, v2
2101; CHECK-FISL-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
2102; CHECK-FISL-NEXT:    addi r3, r3, .LCPI60_0@toc@l
2103; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
2104; CHECK-FISL-NEXT:    vperm v2, v3, v3, v2
2105; CHECK-FISL-NEXT:    xxlor v2, v2, v3
2106; CHECK-FISL-NEXT:    blr
2107;
2108; CHECK-LE-LABEL: test66:
2109; CHECK-LE:       # %bb.0:
2110; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
2111; CHECK-LE-NEXT:    xxlnor v2, v2, v2
2112; CHECK-LE-NEXT:    blr
2113  %w = icmp ne <2 x i64> %a, %b
2114  ret <2 x i1> %w
2115
2116
2117
2118}
2119
2120define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
2121; CHECK-LABEL: test67:
2122; CHECK:       # %bb.0:
2123; CHECK-NEXT:    addi r3, r1, -32
2124; CHECK-NEXT:    stxvd2x v3, 0, r3
2125; CHECK-NEXT:    addi r3, r1, -48
2126; CHECK-NEXT:    stxvd2x v2, 0, r3
2127; CHECK-NEXT:    ld r3, -24(r1)
2128; CHECK-NEXT:    ld r4, -40(r1)
2129; CHECK-NEXT:    ld r6, -48(r1)
2130; CHECK-NEXT:    cmpld r4, r3
2131; CHECK-NEXT:    li r3, 0
2132; CHECK-NEXT:    li r4, -1
2133; CHECK-NEXT:    isellt r5, r4, r3
2134; CHECK-NEXT:    std r5, -8(r1)
2135; CHECK-NEXT:    ld r5, -32(r1)
2136; CHECK-NEXT:    cmpld r6, r5
2137; CHECK-NEXT:    isellt r3, r4, r3
2138; CHECK-NEXT:    std r3, -16(r1)
2139; CHECK-NEXT:    addi r3, r1, -16
2140; CHECK-NEXT:    lxvd2x v2, 0, r3
2141; CHECK-NEXT:    blr
2142;
2143; CHECK-REG-LABEL: test67:
2144; CHECK-REG:       # %bb.0:
2145; CHECK-REG-NEXT:    addi r3, r1, -32
2146; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
2147; CHECK-REG-NEXT:    addi r3, r1, -48
2148; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
2149; CHECK-REG-NEXT:    ld r3, -24(r1)
2150; CHECK-REG-NEXT:    ld r4, -40(r1)
2151; CHECK-REG-NEXT:    ld r6, -48(r1)
2152; CHECK-REG-NEXT:    cmpld r4, r3
2153; CHECK-REG-NEXT:    li r3, 0
2154; CHECK-REG-NEXT:    li r4, -1
2155; CHECK-REG-NEXT:    isellt r5, r4, r3
2156; CHECK-REG-NEXT:    std r5, -8(r1)
2157; CHECK-REG-NEXT:    ld r5, -32(r1)
2158; CHECK-REG-NEXT:    cmpld r6, r5
2159; CHECK-REG-NEXT:    isellt r3, r4, r3
2160; CHECK-REG-NEXT:    std r3, -16(r1)
2161; CHECK-REG-NEXT:    addi r3, r1, -16
2162; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2163; CHECK-REG-NEXT:    blr
2164;
2165; CHECK-FISL-LABEL: test67:
2166; CHECK-FISL:       # %bb.0:
2167; CHECK-FISL-NEXT:    addi r3, r1, -32
2168; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
2169; CHECK-FISL-NEXT:    addi r3, r1, -48
2170; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
2171; CHECK-FISL-NEXT:    ld r4, -24(r1)
2172; CHECK-FISL-NEXT:    ld r3, -40(r1)
2173; CHECK-FISL-NEXT:    cmpld r3, r4
2174; CHECK-FISL-NEXT:    li r4, 0
2175; CHECK-FISL-NEXT:    li r3, -1
2176; CHECK-FISL-NEXT:    isellt r5, r3, r4
2177; CHECK-FISL-NEXT:    std r5, -8(r1)
2178; CHECK-FISL-NEXT:    ld r6, -32(r1)
2179; CHECK-FISL-NEXT:    ld r5, -48(r1)
2180; CHECK-FISL-NEXT:    cmpld r5, r6
2181; CHECK-FISL-NEXT:    isellt r3, r3, r4
2182; CHECK-FISL-NEXT:    std r3, -16(r1)
2183; CHECK-FISL-NEXT:    addi r3, r1, -16
2184; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
2185; CHECK-FISL-NEXT:    blr
2186;
2187; CHECK-LE-LABEL: test67:
2188; CHECK-LE:       # %bb.0:
2189; CHECK-LE-NEXT:    vcmpgtud v2, v3, v2
2190; CHECK-LE-NEXT:    blr
2191  %w = icmp ult <2 x i64> %a, %b
2192  ret <2 x i1> %w
2193
2194; This should scalarize, and the current code quality is not good.
2195
2196}
2197
2198define <2 x double> @test68(<2 x i32> %a) {
2199; CHECK-LABEL: test68:
2200; CHECK:       # %bb.0:
2201; CHECK-NEXT:    xxmrghw vs0, v2, v2
2202; CHECK-NEXT:    xvcvsxwdp v2, vs0
2203; CHECK-NEXT:    blr
2204;
2205; CHECK-REG-LABEL: test68:
2206; CHECK-REG:       # %bb.0:
2207; CHECK-REG-NEXT:    xxmrghw vs0, v2, v2
2208; CHECK-REG-NEXT:    xvcvsxwdp v2, vs0
2209; CHECK-REG-NEXT:    blr
2210;
2211; CHECK-FISL-LABEL: test68:
2212; CHECK-FISL:       # %bb.0:
2213; CHECK-FISL-NEXT:    xxmrghw vs0, v2, v2
2214; CHECK-FISL-NEXT:    xvcvsxwdp v2, vs0
2215; CHECK-FISL-NEXT:    blr
2216;
2217; CHECK-LE-LABEL: test68:
2218; CHECK-LE:       # %bb.0:
2219; CHECK-LE-NEXT:    xxmrglw v2, v2, v2
2220; CHECK-LE-NEXT:    xvcvsxwdp v2, v2
2221; CHECK-LE-NEXT:    blr
2222  %w = sitofp <2 x i32> %a to <2 x double>
2223  ret <2 x double> %w
2224
2225
2226}
2227
2228; This gets scalarized so the code isn't great
2229define <2 x double> @test69(<2 x i16> %a) {
2230; CHECK-LABEL: test69:
2231; CHECK:       # %bb.0:
2232; CHECK-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2233; CHECK-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2234; CHECK-NEXT:    lxvw4x v3, 0, r3
2235; CHECK-NEXT:    addi r3, r1, -32
2236; CHECK-NEXT:    vperm v2, v2, v2, v3
2237; CHECK-NEXT:    stxvd2x v2, 0, r3
2238; CHECK-NEXT:    lha r3, -18(r1)
2239; CHECK-NEXT:    std r3, -8(r1)
2240; CHECK-NEXT:    lha r3, -26(r1)
2241; CHECK-NEXT:    std r3, -16(r1)
2242; CHECK-NEXT:    addi r3, r1, -16
2243; CHECK-NEXT:    lxvd2x v2, 0, r3
2244; CHECK-NEXT:    xvcvsxddp v2, v2
2245; CHECK-NEXT:    blr
2246;
2247; CHECK-REG-LABEL: test69:
2248; CHECK-REG:       # %bb.0:
2249; CHECK-REG-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2250; CHECK-REG-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2251; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2252; CHECK-REG-NEXT:    addi r3, r1, -32
2253; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
2254; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
2255; CHECK-REG-NEXT:    lha r3, -18(r1)
2256; CHECK-REG-NEXT:    std r3, -8(r1)
2257; CHECK-REG-NEXT:    lha r3, -26(r1)
2258; CHECK-REG-NEXT:    std r3, -16(r1)
2259; CHECK-REG-NEXT:    addi r3, r1, -16
2260; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2261; CHECK-REG-NEXT:    xvcvsxddp v2, v2
2262; CHECK-REG-NEXT:    blr
2263;
2264; CHECK-FISL-LABEL: test69:
2265; CHECK-FISL:       # %bb.0:
2266; CHECK-FISL-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2267; CHECK-FISL-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2268; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2269; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
2270; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
2271; CHECK-FISL-NEXT:    addi r3, r1, -32
2272; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
2273; CHECK-FISL-NEXT:    lha r3, -18(r1)
2274; CHECK-FISL-NEXT:    std r3, -8(r1)
2275; CHECK-FISL-NEXT:    lha r3, -26(r1)
2276; CHECK-FISL-NEXT:    std r3, -16(r1)
2277; CHECK-FISL-NEXT:    addi r3, r1, -16
2278; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
2279; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
2280; CHECK-FISL-NEXT:    blr
2281;
2282; CHECK-LE-LABEL: test69:
2283; CHECK-LE:       # %bb.0:
2284; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2285; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2286; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
2287; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_1@toc@ha
2288; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_1@toc@l
2289; CHECK-LE-NEXT:    xxswapd v3, vs0
2290; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
2291; CHECK-LE-NEXT:    lxvd2x v3, 0, r3
2292; CHECK-LE-NEXT:    vsld v2, v2, v3
2293; CHECK-LE-NEXT:    vsrad v2, v2, v3
2294; CHECK-LE-NEXT:    xvcvsxddp v2, v2
2295; CHECK-LE-NEXT:    blr
2296  %w = sitofp <2 x i16> %a to <2 x double>
2297  ret <2 x double> %w
2298
2299
2300}
2301
2302; This gets scalarized so the code isn't great
2303define <2 x double> @test70(<2 x i8> %a) {
2304; CHECK-LABEL: test70:
2305; CHECK:       # %bb.0:
2306; CHECK-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2307; CHECK-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2308; CHECK-NEXT:    lxvw4x v3, 0, r3
2309; CHECK-NEXT:    addi r3, r1, -32
2310; CHECK-NEXT:    vperm v2, v2, v2, v3
2311; CHECK-NEXT:    stxvd2x v2, 0, r3
2312; CHECK-NEXT:    ld r3, -24(r1)
2313; CHECK-NEXT:    extsb r3, r3
2314; CHECK-NEXT:    std r3, -8(r1)
2315; CHECK-NEXT:    ld r3, -32(r1)
2316; CHECK-NEXT:    extsb r3, r3
2317; CHECK-NEXT:    std r3, -16(r1)
2318; CHECK-NEXT:    addi r3, r1, -16
2319; CHECK-NEXT:    lxvd2x v2, 0, r3
2320; CHECK-NEXT:    xvcvsxddp v2, v2
2321; CHECK-NEXT:    blr
2322;
2323; CHECK-REG-LABEL: test70:
2324; CHECK-REG:       # %bb.0:
2325; CHECK-REG-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2326; CHECK-REG-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2327; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2328; CHECK-REG-NEXT:    addi r3, r1, -32
2329; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
2330; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
2331; CHECK-REG-NEXT:    ld r3, -24(r1)
2332; CHECK-REG-NEXT:    extsb r3, r3
2333; CHECK-REG-NEXT:    std r3, -8(r1)
2334; CHECK-REG-NEXT:    ld r3, -32(r1)
2335; CHECK-REG-NEXT:    extsb r3, r3
2336; CHECK-REG-NEXT:    std r3, -16(r1)
2337; CHECK-REG-NEXT:    addi r3, r1, -16
2338; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2339; CHECK-REG-NEXT:    xvcvsxddp v2, v2
2340; CHECK-REG-NEXT:    blr
2341;
2342; CHECK-FISL-LABEL: test70:
2343; CHECK-FISL:       # %bb.0:
2344; CHECK-FISL-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2345; CHECK-FISL-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2346; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2347; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
2348; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
2349; CHECK-FISL-NEXT:    addi r3, r1, -32
2350; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
2351; CHECK-FISL-NEXT:    ld r3, -24(r1)
2352; CHECK-FISL-NEXT:    extsb r3, r3
2353; CHECK-FISL-NEXT:    std r3, -8(r1)
2354; CHECK-FISL-NEXT:    ld r3, -32(r1)
2355; CHECK-FISL-NEXT:    extsb r3, r3
2356; CHECK-FISL-NEXT:    std r3, -16(r1)
2357; CHECK-FISL-NEXT:    addi r3, r1, -16
2358; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
2359; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
2360; CHECK-FISL-NEXT:    blr
2361;
2362; CHECK-LE-LABEL: test70:
2363; CHECK-LE:       # %bb.0:
2364; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2365; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2366; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
2367; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_1@toc@ha
2368; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_1@toc@l
2369; CHECK-LE-NEXT:    xxswapd v3, vs0
2370; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
2371; CHECK-LE-NEXT:    lxvd2x v3, 0, r3
2372; CHECK-LE-NEXT:    vsld v2, v2, v3
2373; CHECK-LE-NEXT:    vsrad v2, v2, v3
2374; CHECK-LE-NEXT:    xvcvsxddp v2, v2
2375; CHECK-LE-NEXT:    blr
2376  %w = sitofp <2 x i8> %a to <2 x double>
2377  ret <2 x double> %w
2378
2379
2380}
2381
2382; This gets scalarized so the code isn't great
2383define <2 x i32> @test80(i32 %v) {
2384; CHECK-LABEL: test80:
2385; CHECK:       # %bb.0:
2386; CHECK-NEXT:    sldi r3, r3, 32
2387; CHECK-NEXT:    std r3, -16(r1)
2388; CHECK-NEXT:    std r3, -8(r1)
2389; CHECK-NEXT:    addi r3, r1, -16
2390; CHECK-NEXT:    lxvw4x vs0, 0, r3
2391; CHECK-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2392; CHECK-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2393; CHECK-NEXT:    lxvw4x v3, 0, r3
2394; CHECK-NEXT:    xxspltw v2, vs0, 0
2395; CHECK-NEXT:    vadduwm v2, v2, v3
2396; CHECK-NEXT:    blr
2397;
2398; CHECK-REG-LABEL: test80:
2399; CHECK-REG:       # %bb.0:
2400; CHECK-REG-NEXT:    sldi r3, r3, 32
2401; CHECK-REG-NEXT:    std r3, -16(r1)
2402; CHECK-REG-NEXT:    std r3, -8(r1)
2403; CHECK-REG-NEXT:    addi r3, r1, -16
2404; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
2405; CHECK-REG-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2406; CHECK-REG-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2407; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2408; CHECK-REG-NEXT:    xxspltw v2, vs0, 0
2409; CHECK-REG-NEXT:    vadduwm v2, v2, v3
2410; CHECK-REG-NEXT:    blr
2411;
2412; CHECK-FISL-LABEL: test80:
2413; CHECK-FISL:       # %bb.0:
2414; CHECK-FISL-NEXT:    mr r4, r3
2415; CHECK-FISL-NEXT:    # implicit-def: $x3
2416; CHECK-FISL-NEXT:    mr r3, r4
2417; CHECK-FISL-NEXT:    sldi r3, r3, 32
2418; CHECK-FISL-NEXT:    std r3, -8(r1)
2419; CHECK-FISL-NEXT:    std r3, -16(r1)
2420; CHECK-FISL-NEXT:    addi r3, r1, -16
2421; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
2422; CHECK-FISL-NEXT:    xxspltw v2, vs0, 0
2423; CHECK-FISL-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2424; CHECK-FISL-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2425; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2426; CHECK-FISL-NEXT:    vadduwm v2, v2, v3
2427; CHECK-FISL-NEXT:    blr
2428;
2429; CHECK-LE-LABEL: test80:
2430; CHECK-LE:       # %bb.0:
2431; CHECK-LE-NEXT:    mtfprwz f0, r3
2432; CHECK-LE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2433; CHECK-LE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2434; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
2435; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
2436; CHECK-LE-NEXT:    xxswapd v3, vs0
2437; CHECK-LE-NEXT:    vadduwm v2, v2, v3
2438; CHECK-LE-NEXT:    blr
2439  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
2440  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
2441  %i = add <2 x i32> %b2, <i32 2, i32 3>
2442  ret <2 x i32> %i
2443
2444
2445
2446}
2447
2448define <2 x double> @test81(<4 x float> %b) {
2449; CHECK-LABEL: test81:
2450; CHECK:       # %bb.0:
2451; CHECK-NEXT:    blr
2452;
2453; CHECK-REG-LABEL: test81:
2454; CHECK-REG:       # %bb.0:
2455; CHECK-REG-NEXT:    blr
2456;
2457; CHECK-FISL-LABEL: test81:
2458; CHECK-FISL:       # %bb.0:
2459; CHECK-FISL-NEXT:    blr
2460;
2461; CHECK-LE-LABEL: test81:
2462; CHECK-LE:       # %bb.0:
2463; CHECK-LE-NEXT:    blr
2464  %w = bitcast <4 x float> %b to <2 x double>
2465  ret <2 x double> %w
2466
2467
2468}
2469
2470define double @test82(double %a, double %b, double %c, double %d) {
2471; CHECK-LABEL: test82:
2472; CHECK:       # %bb.0: # %entry
2473; CHECK-NEXT:    xscmpudp cr0, f3, f4
2474; CHECK-NEXT:    beqlr cr0
2475; CHECK-NEXT:  # %bb.1: # %entry
2476; CHECK-NEXT:    fmr f1, f2
2477; CHECK-NEXT:    blr
2478;
2479; CHECK-REG-LABEL: test82:
2480; CHECK-REG:       # %bb.0: # %entry
2481; CHECK-REG-NEXT:    xscmpudp cr0, f3, f4
2482; CHECK-REG-NEXT:    beqlr cr0
2483; CHECK-REG-NEXT:  # %bb.1: # %entry
2484; CHECK-REG-NEXT:    fmr f1, f2
2485; CHECK-REG-NEXT:    blr
2486;
2487; CHECK-FISL-LABEL: test82:
2488; CHECK-FISL:       # %bb.0: # %entry
2489; CHECK-FISL-NEXT:    stfd f2, -16(r1) # 8-byte Folded Spill
2490; CHECK-FISL-NEXT:    fmr f2, f1
2491; CHECK-FISL-NEXT:    xscmpudp cr0, f3, f4
2492; CHECK-FISL-NEXT:    stfd f2, -8(r1) # 8-byte Folded Spill
2493; CHECK-FISL-NEXT:    beq cr0, .LBB67_2
2494; CHECK-FISL-NEXT:  # %bb.1: # %entry
2495; CHECK-FISL-NEXT:    lfd f0, -16(r1) # 8-byte Folded Reload
2496; CHECK-FISL-NEXT:    stfd f0, -8(r1) # 8-byte Folded Spill
2497; CHECK-FISL-NEXT:  .LBB67_2: # %entry
2498; CHECK-FISL-NEXT:    lfd f1, -8(r1) # 8-byte Folded Reload
2499; CHECK-FISL-NEXT:    blr
2500;
2501; CHECK-LE-LABEL: test82:
2502; CHECK-LE:       # %bb.0: # %entry
2503; CHECK-LE-NEXT:    xscmpudp cr0, f3, f4
2504; CHECK-LE-NEXT:    beqlr cr0
2505; CHECK-LE-NEXT:  # %bb.1: # %entry
2506; CHECK-LE-NEXT:    fmr f1, f2
2507; CHECK-LE-NEXT:    blr
2508entry:
2509  %m = fcmp oeq double %c, %d
2510  %v = select i1 %m, double %a, double %b
2511  ret double %v
2512
2513
2514
2515}
2516