1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \ 2; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \ 4; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ 5; RUN: -check-prefix=CHECK-REG %s 6; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \ 7; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s 8; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \ 9; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \ 10; RUN: FileCheck -check-prefix=CHECK-FISL %s 11; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 12; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s 13; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \ 14; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ 15; RUN: -check-prefix=CHECK-P9-FISL %s 16target datalayout = "E-m:e-i64:64-n32:64" 17target triple = "powerpc64-unknown-linux-gnu" 18 19define double @foo1(double %a) nounwind { 20entry: 21 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind 22 br label %return 23 24; CHECK-REG: @foo1 25; CHECK-REG: xxlor v2, f1, f1 26; CHECK-REG: xxlor f1, v2, v2 27; CHECK-REG: blr 28 29; CHECK-FISL: @foo1 30; CHECK-FISL-NOT: lis 31; CHECK-FISL-NOT: ori 32; CHECK-FISL: li r3, -152 33; CHECK-FISL-NOT: lis 34; CHECK-FISL-NOT: ori 35; CHECK-FISL: stxsdx f1, r1, r3 36; CHECK-FISL: blr 37 38; CHECK-P9-REG: @foo1 39; CHECK-P9-REG: xscpsgndp v2, f1, f1 40; CHECK-P9-REG: xscpsgndp f1, v2, v2 41; CHECK-P9-REG: blr 42 43; CHECK-P9-FISL: @foo1 44; CHECK-P9-FISL: stfd f31, -8(r1) 45; CHECK-P9-FISL: blr 46 47return: ; preds = %entry 48 ret double %a 49} 50 51define double @foo2(double %a) nounwind { 52entry: 53 %b = fadd double %a, %a 54 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind 55 br label %return 56 57; CHECK-REG: @foo2 58; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f1 59; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f0 60; CHECK-REG: blr 61 62; CHECK-FISL: @foo2 63; CHECK-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1 64; CHECK-FISL: stxsdx [[REG0]], r1, r3 65; CHECK-FISL: lxsdx f1, r1, r3 66; CHECK-FISL: blr 67 68; CHECK-P9-REG: @foo2 69; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f1 70; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v2 71; CHECK-P9-REG: blr 72 73; CHECK-P9-FISL: @foo2 74; CHECK-P9-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1 75; CHECK-P9-FISL: stfd [[REG0]], -152(r1) 76; CHECK-P9-FISL: lfd f1, -152(r1) 77; CHECK-P9-FISL: blr 78 79return: ; preds = %entry 80 ret double %b 81} 82 83define double @foo3(double %a) nounwind { 84entry: 85 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind 86 br label %return 87 88; CHECK: @foo3 89; CHECK: stxsdx f1, r1, r3 90; CHECK: lxsdx f0, r1, r3 91; CHECK: xsadddp f1, f0, f0 92; CHECK: blr 93 94; CHECK-P9-REG-LABEL: foo3 95; CHECK-P9-REG: stdu r1, -400(r1) 96; CHECK-P9-REG-DAG: lfd f30, 384(r1) 97; CHECK-P9-REG-DAG: xsadddp f1, f0, f0 98 99; CHECK-P9-FISL-LABEL: foo3 100; CHECK-P9-FISL: stdu r1, -400(r1) 101; CHECK-P9-FISL: lfd f0, 56(r1) 102; CHECK-P9-FISL: xsadddp f1, f0, f0 103return: ; preds = %entry 104 %b = fadd double %a, %a 105 ret double %b 106} 107 108