xref: /llvm-project/llvm/test/CodeGen/PowerPC/vselect-constants.ll (revision b922a3621116b404d868af8b74cab25ab78555be) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
3
4; First, check the generic pattern for any 2 vector constants. Then, check special cases where
5; the constants are all off-by-one. Finally, check the extra special cases where the constants
6; include 0 or -1.
7; Each minimal select test is repeated with a more typical pattern that includes a compare to
8; generate the condition value.
9
10define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
11; CHECK-LABEL: sel_C1_or_C2_vec:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
14; CHECK-NEXT:    vspltisw 3, -16
15; CHECK-NEXT:    vspltisw 4, 15
16; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
17; CHECK-NEXT:    vsubuwm 3, 4, 3
18; CHECK-NEXT:    lxvd2x 0, 0, 3
19; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
20; CHECK-NEXT:    vslw 2, 2, 3
21; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
22; CHECK-NEXT:    vsraw 2, 2, 3
23; CHECK-NEXT:    xxswapd 37, 0
24; CHECK-NEXT:    lxvd2x 0, 0, 3
25; CHECK-NEXT:    xxswapd 32, 0
26; CHECK-NEXT:    xxsel 34, 32, 37, 34
27; CHECK-NEXT:    blr
28  %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
29  ret <4 x i32> %add
30}
31
32define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
33; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
36; CHECK-NEXT:    vcmpequw 2, 2, 3
37; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
38; CHECK-NEXT:    lxvd2x 0, 0, 3
39; CHECK-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
40; CHECK-NEXT:    addi 3, 3, .LCPI1_1@toc@l
41; CHECK-NEXT:    xxswapd 36, 0
42; CHECK-NEXT:    lxvd2x 0, 0, 3
43; CHECK-NEXT:    xxswapd 37, 0
44; CHECK-NEXT:    xxsel 34, 37, 36, 34
45; CHECK-NEXT:    blr
46  %cond = icmp eq <4 x i32> %x, %y
47  %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
48  ret <4 x i32> %add
49}
50
51define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
52; CHECK-LABEL: sel_Cplus1_or_C_vec:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
55; CHECK-NEXT:    vspltisw 3, 1
56; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
57; CHECK-NEXT:    xxland 34, 34, 35
58; CHECK-NEXT:    lxvd2x 0, 0, 3
59; CHECK-NEXT:    xxswapd 36, 0
60; CHECK-NEXT:    vadduwm 2, 2, 4
61; CHECK-NEXT:    blr
62  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
63  ret <4 x i32> %add
64}
65
66define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
67; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
70; CHECK-NEXT:    vcmpequw 2, 2, 3
71; CHECK-NEXT:    addi 3, 3, .LCPI3_0@toc@l
72; CHECK-NEXT:    lxvd2x 0, 0, 3
73; CHECK-NEXT:    xxswapd 36, 0
74; CHECK-NEXT:    vsubuwm 2, 4, 2
75; CHECK-NEXT:    blr
76  %cond = icmp eq <4 x i32> %x, %y
77  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
78  ret <4 x i32> %add
79}
80
81define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
82; CHECK-LABEL: sel_Cminus1_or_C_vec:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
85; CHECK-NEXT:    vspltisw 3, -16
86; CHECK-NEXT:    vspltisw 4, 15
87; CHECK-NEXT:    addi 3, 3, .LCPI4_0@toc@l
88; CHECK-NEXT:    vsubuwm 3, 4, 3
89; CHECK-NEXT:    lxvd2x 0, 0, 3
90; CHECK-NEXT:    vslw 2, 2, 3
91; CHECK-NEXT:    vsraw 2, 2, 3
92; CHECK-NEXT:    xxswapd 37, 0
93; CHECK-NEXT:    vadduwm 2, 2, 5
94; CHECK-NEXT:    blr
95  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
96  ret <4 x i32> %add
97}
98
99define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
100; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
103; CHECK-NEXT:    vcmpequw 2, 2, 3
104; CHECK-NEXT:    addi 3, 3, .LCPI5_0@toc@l
105; CHECK-NEXT:    lxvd2x 0, 0, 3
106; CHECK-NEXT:    xxswapd 36, 0
107; CHECK-NEXT:    vadduwm 2, 2, 4
108; CHECK-NEXT:    blr
109  %cond = icmp eq <4 x i32> %x, %y
110  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
111  ret <4 x i32> %add
112}
113
114define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
115; CHECK-LABEL: sel_minus1_or_0_vec:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vspltisw 3, -16
118; CHECK-NEXT:    vspltisw 4, 15
119; CHECK-NEXT:    vsubuwm 3, 4, 3
120; CHECK-NEXT:    vslw 2, 2, 3
121; CHECK-NEXT:    vsraw 2, 2, 3
122; CHECK-NEXT:    blr
123  %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
124  ret <4 x i32> %add
125}
126
127define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
128; CHECK-LABEL: cmp_sel_minus1_or_0_vec:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vcmpequw 2, 2, 3
131; CHECK-NEXT:    blr
132  %cond = icmp eq <4 x i32> %x, %y
133  %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
134  ret <4 x i32> %add
135}
136
137define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
138; CHECK-LABEL: sel_0_or_minus1_vec:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vspltisw 3, 1
141; CHECK-NEXT:    xxland 34, 34, 35
142; CHECK-NEXT:    xxleqv 35, 35, 35
143; CHECK-NEXT:    vadduwm 2, 2, 3
144; CHECK-NEXT:    blr
145  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
146  ret <4 x i32> %add
147}
148
149define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
150; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vcmpequw 2, 2, 3
153; CHECK-NEXT:    xxlnor 34, 34, 34
154; CHECK-NEXT:    blr
155  %cond = icmp eq <4 x i32> %x, %y
156  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
157  ret <4 x i32> %add
158}
159
160define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
161; CHECK-LABEL: sel_1_or_0_vec:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vspltisw 3, 1
164; CHECK-NEXT:    xxland 34, 34, 35
165; CHECK-NEXT:    blr
166  %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
167  ret <4 x i32> %add
168}
169
170define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
171; CHECK-LABEL: cmp_sel_1_or_0_vec:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vspltisw 4, 1
174; CHECK-NEXT:    vcmpequw 2, 2, 3
175; CHECK-NEXT:    xxland 34, 34, 36
176; CHECK-NEXT:    blr
177  %cond = icmp eq <4 x i32> %x, %y
178  %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
179  ret <4 x i32> %add
180}
181
182define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
183; CHECK-LABEL: sel_0_or_1_vec:
184; CHECK:       # %bb.0:
185; CHECK-NEXT:    vspltisw 3, 1
186; CHECK-NEXT:    xxlandc 34, 35, 34
187; CHECK-NEXT:    blr
188  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
189  ret <4 x i32> %add
190}
191
192define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
193; CHECK-LABEL: cmp_sel_0_or_1_vec:
194; CHECK:       # %bb.0:
195; CHECK-NEXT:    vcmpequw 2, 2, 3
196; CHECK-NEXT:    vspltisw 4, 1
197; CHECK-NEXT:    xxlnor 0, 34, 34
198; CHECK-NEXT:    xxland 34, 0, 36
199; CHECK-NEXT:    blr
200  %cond = icmp eq <4 x i32> %x, %y
201  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
202  ret <4 x i32> %add
203}
204
205