xref: /llvm-project/llvm/test/CodeGen/PowerPC/vector-sum-sat-bit-side-effect.ll (revision a3b57bca97c0bf56ee1db319a5ff633b516f927e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix-xcoff \
5; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
6; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix-xcoff \
7; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
8
9define void @test1(<16 x i8> %0) {
10; CHECK-LABEL: test1:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    blr
13entry:
14  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)
15  ret void
16}
17
18define void @test2(<8 x i16> %0) {
19; CHECK-LABEL: test2:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    blr
22entry:
23  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)
24  ret void
25}
26
27define void @test3(<16 x i8> %0) {
28; CHECK-LABEL: test3:
29; CHECK:       # %bb.0: # %entry
30; CHECK-NEXT:    blr
31entry:
32  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
33  ret void
34}
35
36define void @test4(<16 x i8> %0) {
37; CHECK-LABEL: test4:
38; CHECK:       # %bb.0: # %entry
39; CHECK-NEXT:    vspltisw v3, 1
40; CHECK-NEXT:    vsum4sbs v2, v2, v3
41; CHECK-NEXT:    blr
42entry:
43  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
44  ret void
45}
46
47define void @test5(<8 x i16> %0) {
48; CHECK-LABEL: test5:
49; CHECK:       # %bb.0: # %entry
50; CHECK-NEXT:    vspltisw v3, 1
51; CHECK-NEXT:    vsum4shs v2, v2, v3
52; CHECK-NEXT:    blr
53entry:
54  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
55  ret void
56}
57
58define void @test6(<16 x i8> %0) {
59; CHECK-LABEL: test6:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    vspltisw v3, 1
62; CHECK-NEXT:    vsum4ubs v2, v2, v3
63; CHECK-NEXT:    blr
64entry:
65  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
66  ret void
67}
68
69define <4 x i32> @test7(<16 x i8> %0) {
70; CHECK-LABEL: test7:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    xxlxor v3, v3, v3
73; CHECK-NEXT:    vsum4sbs v2, v2, v3
74; CHECK-NEXT:    blr
75entry:
76  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)
77  ret <4 x i32> %1
78}
79
80define <4 x i32> @test8(<8 x i16> %0) {
81; CHECK-LABEL: test8:
82; CHECK:       # %bb.0: # %entry
83; CHECK-NEXT:    xxlxor v3, v3, v3
84; CHECK-NEXT:    vsum4shs v2, v2, v3
85; CHECK-NEXT:    blr
86entry:
87  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)
88  ret <4 x i32> %1
89}
90
91define <4 x i32> @test9(<16 x i8> %0) {
92; CHECK-LABEL: test9:
93; CHECK:       # %bb.0: # %entry
94; CHECK-NEXT:    xxlxor v3, v3, v3
95; CHECK-NEXT:    vsum4ubs v2, v2, v3
96; CHECK-NEXT:    blr
97entry:
98  %1 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
99  ret <4 x i32> %1
100}
101
102define <4 x i32> @test10(<16 x i8> %0, <16 x i8> %1) {
103; CHECK-LABEL: test10:
104; CHECK:       # %bb.0: # %entry
105; CHECK-NEXT:    xxlxor v3, v3, v3
106; CHECK-NEXT:    vsum4sbs v2, v2, v3
107; CHECK-NEXT:    blr
108entry:
109  %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %0, <4 x i32> zeroinitializer)
110  %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8> %1, <4 x i32> zeroinitializer)
111  ret <4 x i32> %2
112}
113
114define <4 x i32> @test11(<8 x i16> %0, <8 x i16> %1) {
115; CHECK-LABEL: test11:
116; CHECK:       # %bb.0: # %entry
117; CHECK-NEXT:    xxlxor v3, v3, v3
118; CHECK-NEXT:    vsum4shs v2, v2, v3
119; CHECK-NEXT:    blr
120entry:
121  %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %0, <4 x i32> zeroinitializer)
122  %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16> %1, <4 x i32> zeroinitializer)
123  ret <4 x i32> %2
124}
125
126define <4 x i32> @test12(<16 x i8> %0, <16 x i8> %1) {
127; CHECK-LABEL: test12:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    xxlxor v3, v3, v3
130; CHECK-NEXT:    vsum4ubs v2, v2, v3
131; CHECK-NEXT:    blr
132entry:
133  %2 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %0, <4 x i32> zeroinitializer)
134  %3 = tail call <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8> %1, <4 x i32> zeroinitializer)
135  ret <4 x i32> %2
136}
137
138declare <4 x i32> @llvm.ppc.altivec.vsum4sbs(<16 x i8>, <4 x i32>)
139declare <4 x i32> @llvm.ppc.altivec.vsum4shs(<8 x i16>, <4 x i32>)
140declare <4 x i32> @llvm.ppc.altivec.vsum4ubs(<16 x i8>, <4 x i32>)
141